Reworked storage architecture (moved I/O memory to a separate module, since there's

only one instance of input/output values, while storage manager has dual storage space
for P and Q multipliers).

Started working on microcoded layer, added input operation and modular multiplication.

1 files changed, 100 insertions, 39 deletions

diff --git a/rtl/modexpng_reductor.v b/rtl/modexpng_reductor.v
index aafb38c..a37333e 100644
--- a/rtl/modexpng_reductor.v
+++ b/rtl/modexpng_reductor.v
@@ -2,18 +2,14 @@ module modexpng_reductor
 (
     clk, rst,
     ena, rdy,
-    //fsm_state_next,
     word_index_last,
-    //dsp_xy_ce_p,
-    //dsp_x_p, dsp_y_p,
-    //col_index, col_index_last,
+    sel_wide_out, sel_narrow_out,
     rd_wide_xy_addr_aux, rd_wide_xy_bank_aux, rd_wide_x_dout_aux, rd_wide_y_dout_aux,
-    //rcmb_wide_xy_bank,   rcmb_wide_xy_addr,   rcmb_wide_x_dout,   rcmb_wide_y_dout,   rcmb_wide_xy_valid,
-    rcmb_final_xy_bank, rcmb_final_xy_addr, rcmb_final_x_dout, rcmb_final_y_dout, rcmb_final_xy_valid,
-                        rdct_final_xy_addr, rdct_final_x_dout, rdct_final_y_dout, rdct_final_xy_valid
+    rcmb_final_xy_bank,  rcmb_final_xy_addr,  rcmb_final_x_dout,  rcmb_final_y_dout,  rcmb_final_xy_valid,
+    rdct_wide_xy_bank,   rdct_wide_xy_addr,   rdct_wide_x_dout,   rdct_wide_y_dout,   rdct_wide_xy_valid,
+    rdct_narrow_xy_bank, rdct_narrow_xy_addr, rdct_narrow_x_dout, rdct_narrow_y_dout, rdct_narrow_xy_valid
 );
 
-
     //
     // Headers
     //
@@ -31,7 +27,10 @@ module modexpng_reductor
     input  [FSM_STATE_WIDTH-1:0] fsm_state_next;*/
     input [7:0]                  word_index_last;/*
     input                        dsp_xy_ce_p;
-    *//*
+    */
+    input [2:0] sel_wide_out;
+    input [2:0] sel_narrow_out;
+    /*
     input  [9*47-1:0] dsp_x_p;
     input  [9*47-1:0] dsp_y_p;
     input  [     4:0] col_index;
@@ -51,11 +50,17 @@ module modexpng_reductor
     input  [    17:0] rcmb_final_y_dout;
     input             rcmb_final_xy_valid;
 
-    output [     7:0] rdct_final_xy_addr;
-    output [    17:0] rdct_final_x_dout;
-    output [    17:0] rdct_final_y_dout;
-    output            rdct_final_xy_valid;
+    output [     2:0] rdct_wide_xy_bank;
+    output [     7:0] rdct_wide_xy_addr;
+    output [    17:0] rdct_wide_x_dout;
+    output [    17:0] rdct_wide_y_dout;
+    output            rdct_wide_xy_valid;
 
+    output [     2:0] rdct_narrow_xy_bank;
+    output [     7:0] rdct_narrow_xy_addr;
+    output [    17:0] rdct_narrow_x_dout;
+    output [    17:0] rdct_narrow_y_dout;
+    output            rdct_narrow_xy_valid;
 
     //
     // Ready
@@ -178,41 +183,89 @@ module modexpng_reductor
     //
     // Reduction
     //
-    reg [     7:0] rdct_xy_addr;
-    reg [    17:0] rdct_x_dout;
-    reg [    17:0] rdct_y_dout;
-    reg            rdct_xy_valid = 1'b0;
+    reg [     2:0] wide_xy_bank;
+    reg [     7:0] wide_xy_addr;
+    reg [    17:0] wide_x_dout;
+    reg [    17:0] wide_y_dout;
+    reg            wide_xy_valid = 1'b0;
 
-    assign rdct_final_xy_addr  = rdct_xy_addr;
-    assign rdct_final_x_dout   = rdct_x_dout;
-    assign rdct_final_y_dout   = rdct_y_dout;
-    assign rdct_final_xy_valid = rdct_xy_valid;
+    reg [     2:0] narrow_xy_bank;
+    reg [     7:0] narrow_xy_addr;
+    reg [    17:0] narrow_x_dout;
+    reg [    17:0] narrow_y_dout;
+    reg            narrow_xy_valid = 1'b0;
 
-    task _update_rdct;
+    assign rdct_wide_xy_bank  = wide_xy_bank;
+    assign rdct_wide_xy_addr  = wide_xy_addr;
+    assign rdct_wide_x_dout   = wide_x_dout;
+    assign rdct_wide_y_dout   = wide_y_dout;
+    assign rdct_wide_xy_valid = wide_xy_valid;
+
+    assign rdct_narrow_xy_bank  = narrow_xy_bank;
+    assign rdct_narrow_xy_addr  = narrow_xy_addr;
+    assign rdct_narrow_x_dout   = narrow_x_dout;
+    assign rdct_narrow_y_dout   = narrow_y_dout;
+    assign rdct_narrow_xy_valid = narrow_xy_valid;
+
+    task _update_rdct_wide;
+        input [ 2:0] bank;
         input [ 7:0] addr;
         input [17:0] dout_x;
         input [17:0] dout_y;
         input        valid;
         begin
-            rdct_xy_addr  <= addr;
-            rdct_x_dout   <= dout_x;
-            rdct_y_dout   <= dout_y;
-            rdct_xy_valid <= valid;
+            wide_xy_bank  <= bank;
+            wide_xy_addr  <= addr;
+            wide_x_dout   <= dout_x;
+            wide_y_dout   <= dout_y;
+            wide_xy_valid <= valid;
         end
     endtask
     
-    task set_rdct;
+    task _update_rdct_narrow;
+        input [ 2:0] bank;
         input [ 7:0] addr;
         input [17:0] dout_x;
         input [17:0] dout_y;
+        input        valid;
         begin
-            _update_rdct(addr, dout_x, dout_y, 1'b1);
+            narrow_xy_bank  <= bank;
+            narrow_xy_addr  <= addr;
+            narrow_x_dout   <= dout_x;
+            narrow_y_dout   <= dout_y;
+            narrow_xy_valid <= valid;
         end
     endtask
     
-    task clear_rdct;
+    task set_rdct_wide;
+        input [ 2:0] bank;
+        input [ 7:0] addr;
+        input [17:0] dout_x;
+        input [17:0] dout_y;
         begin
-            _update_rdct(8'hXX, {18{1'bX}}, {18{1'bX}}, 1'b0);
+            _update_rdct_wide(bank, addr, dout_x, dout_y, 1'b1);
+        end
+    endtask
+    
+    task set_rdct_narrow;
+        input [ 2:0] bank;
+        input [ 7:0] addr;
+        input [17:0] dout_x;
+        input [17:0] dout_y;
+        begin
+            _update_rdct_narrow(bank, addr, dout_x, dout_y, 1'b1);
+        end
+    endtask
+    
+    task clear_rdct_wide;
+        begin
+            _update_rdct_wide(3'bXXX, 8'hXX, {18{1'bX}}, {18{1'bX}}, 1'b0);
+        end
+    endtask
+
+    task clear_rdct_narrow;
+        begin
+            _update_rdct_narrow(3'bXXX, 8'hXX, {18{1'bX}}, {18{1'bX}}, 1'b0);
         end
     endtask
     
@@ -232,23 +285,31 @@ module modexpng_reductor
     //
     always @(posedge clk)
         //
-        if (rst) clear_rdct;
-        else begin
+        if (rst) begin
+            clear_rdct_wide;
+            clear_rdct_narrow;
+        end else begin
             //
-            clear_rdct;
+            clear_rdct_wide;
+            clear_rdct_narrow;
             //
             if (rcmb_xy_valid_dly3)
                 //
                 case (rcmb_xy_bank_dly3)
                                     
                     BANK_RCMB_MH:
-                        if (rcmb_xy_addr_dly3 == 8'd1)
-                            set_rdct(8'd0, sum_rdct_x_carry, sum_rdct_y_carry);
-                        else if (rcmb_xy_addr_dly3 > 8'd1)
-                            set_rdct(rcmb_xy_addr_dly3 - 1'b1, sum_rdct_x, sum_rdct_y);
+                        if (rcmb_xy_addr_dly3 == 8'd1) begin
+                            set_rdct_wide  (sel_wide_out,   8'd0, sum_rdct_x_carry, sum_rdct_y_carry);
+                            set_rdct_narrow(sel_narrow_out, 8'd0, sum_rdct_x_carry, sum_rdct_y_carry);
+                        end else if (rcmb_xy_addr_dly3 > 8'd1) begin
+                            set_rdct_wide  (sel_wide_out,   rcmb_xy_addr_dly3 - 1'b1, sum_rdct_x, sum_rdct_y);
+                            set_rdct_narrow(sel_narrow_out, rcmb_xy_addr_dly3 - 1'b1, sum_rdct_x, sum_rdct_y);
+                        end
                             
-                    BANK_RCMB_EXT:
-                        set_rdct(word_index_last, rcmb_x_dout_dly3, rcmb_y_dout_dly3);
+                    BANK_RCMB_EXT: begin
+                        set_rdct_wide  (sel_wide_out,   word_index_last, rcmb_x_dout_dly3, rcmb_y_dout_dly3);
+                        set_rdct_narrow(sel_narrow_out, word_index_last, rcmb_x_dout_dly3, rcmb_y_dout_dly3);
+                    end
 
                 endcase
             //