diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-03 16:47:39 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-03 16:47:39 +0300 |
| commit | e340b1489b08905e3d8acd17686e178028de7922 (patch) | |
| tree | 8804029e5fcad42a52745fe7951ac4d203ba3c35 /rtl/modexpng_reductor.v | |
| parent | 8ee5a19240722f397d55f57a426992350f8019a3 (diff) | |
Added more micro-operations, also added "general worker" module. The worker is basically
a block memory data mover, but it can also do some supporting operations required for the
Garner's formula part of the exponentiation.
Diffstat (limited to 'rtl/modexpng_reductor.v')
| -rw-r--r-- | rtl/modexpng_reductor.v | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/rtl/modexpng_reductor.v b/rtl/modexpng_reductor.v index a37333e..c100b8b 100644 --- a/rtl/modexpng_reductor.v +++ b/rtl/modexpng_reductor.v @@ -4,8 +4,8 @@ module modexpng_reductor ena, rdy, word_index_last, sel_wide_out, sel_narrow_out, - rd_wide_xy_addr_aux, rd_wide_xy_bank_aux, rd_wide_x_dout_aux, rd_wide_y_dout_aux, - rcmb_final_xy_bank, rcmb_final_xy_addr, rcmb_final_x_dout, rcmb_final_y_dout, rcmb_final_xy_valid, + rd_wide_xy_addr_aux, rd_wide_xy_bank_aux, rd_wide_x_din_aux, rd_wide_y_din_aux, + rcmb_final_xy_bank, rcmb_final_xy_addr, rcmb_final_x_din, rcmb_final_y_din, rcmb_final_xy_valid, rdct_wide_xy_bank, rdct_wide_xy_addr, rdct_wide_x_dout, rdct_wide_y_dout, rdct_wide_xy_valid, rdct_narrow_xy_bank, rdct_narrow_xy_addr, rdct_narrow_x_dout, rdct_narrow_y_dout, rdct_narrow_xy_valid ); @@ -41,13 +41,13 @@ module modexpng_reductor */ input [ BANK_ADDR_W -1:0] rd_wide_xy_bank_aux; input [ 7:0] rd_wide_xy_addr_aux; - input [ 17:0] rd_wide_x_dout_aux; - input [ 17:0] rd_wide_y_dout_aux; + input [ 17:0] rd_wide_x_din_aux; + input [ 17:0] rd_wide_y_din_aux; // input [ BANK_ADDR_W -1:0] rcmb_final_xy_bank; input [ 7:0] rcmb_final_xy_addr; - input [ 17:0] rcmb_final_x_dout; - input [ 17:0] rcmb_final_y_dout; + input [ 17:0] rcmb_final_x_din; + input [ 17:0] rcmb_final_y_din; input rcmb_final_xy_valid; output [ 2:0] rdct_wide_xy_bank; @@ -121,8 +121,8 @@ module modexpng_reductor if (rcmb_final_xy_valid) begin rcmb_xy_bank_dly1 <= rcmb_final_xy_bank; rcmb_xy_addr_dly1 <= rcmb_final_xy_addr; - rcmb_x_dout_dly1 <= rcmb_final_x_dout; - rcmb_y_dout_dly1 <= rcmb_final_y_dout; + rcmb_x_dout_dly1 <= rcmb_final_x_din; + rcmb_y_dout_dly1 <= rcmb_final_y_din; end // if (rcmb_xy_valid_dly1) begin @@ -167,14 +167,14 @@ module modexpng_reductor case (rcmb_xy_bank_dly3) BANK_RCMB_ML: begin - {rcmb_x_lsb_carry, rcmb_x_lsb_dummy} <= rcmb_x_dout_dly3 + rd_wide_x_dout_aux + rcmb_x_lsb_carry; - {rcmb_y_lsb_carry, rcmb_y_lsb_dummy} <= rcmb_y_dout_dly3 + rd_wide_y_dout_aux + rcmb_y_lsb_carry; + {rcmb_x_lsb_carry, rcmb_x_lsb_dummy} <= rcmb_x_dout_dly3 + rd_wide_x_din_aux + rcmb_x_lsb_carry; + {rcmb_y_lsb_carry, rcmb_y_lsb_dummy} <= rcmb_y_dout_dly3 + rd_wide_y_din_aux + rcmb_y_lsb_carry; end BANK_RCMB_MH: if (rcmb_xy_addr_dly3 == 8'd0) begin - {rcmb_x_lsb_carry, rcmb_x_lsb_dummy} <= rcmb_x_dout_dly3 + rd_wide_x_dout_aux + rcmb_x_lsb_carry; - {rcmb_y_lsb_carry, rcmb_y_lsb_dummy} <= rcmb_y_dout_dly3 + rd_wide_y_dout_aux + rcmb_y_lsb_carry; + {rcmb_x_lsb_carry, rcmb_x_lsb_dummy} <= rcmb_x_dout_dly3 + rd_wide_x_din_aux + rcmb_x_lsb_carry; + {rcmb_y_lsb_carry, rcmb_y_lsb_dummy} <= rcmb_y_dout_dly3 + rd_wide_y_din_aux + rcmb_y_lsb_carry; end endcase @@ -273,8 +273,8 @@ module modexpng_reductor // // // - wire [17:0] sum_rdct_x = rcmb_x_dout_dly3 + rd_wide_x_dout_aux; - wire [17:0] sum_rdct_y = rcmb_y_dout_dly3 + rd_wide_y_dout_aux; + wire [17:0] sum_rdct_x = rcmb_x_dout_dly3 + rd_wide_x_din_aux; + wire [17:0] sum_rdct_y = rcmb_y_dout_dly3 + rd_wide_y_din_aux; wire [17:0] sum_rdct_x_carry = sum_rdct_x + {16'h0000, rcmb_x_lsb_carry}; wire [17:0] sum_rdct_y_carry = sum_rdct_y + {16'h0000, rcmb_y_lsb_carry}; |