core/comm/uart - A Universal asynchronous receiver/transmitter (UART) implemented in Verilog

Age	Commit message (Collapse)	Author
2015-12-13	whack copyrightsHEAD master	Paul Selkirk

2015-03-31	Fix testbench to match new file organization.	Paul Selkirk

2015-03-31	Don't delay register reads in uart_regs.	Paul Selkirk

2015-03-17	Rearrange cores.	Paul Selkirk

2014-11-07	Changed to asynch reset.	Joachim Strömbergson

2014-05-09	Update of core address size to 8 bits. Changed use of bit rate, data and ↵	Joachim Strömbergson
	stop bits from the top.
2014-05-09	Update of core to use bitrate, data bits and stop bits supplied via ports.	Joachim Strömbergson

2014-05-09	Adding support for setting bit rate, data- and stop bits.	Joachim Strömbergson

2014-03-17	Changing from blocking to correct, non-blocking assignments in reg update.	Joachim Strömbergson

2014-03-17	Adding size constraints to constant definitions to remove synthesis warnings.	Joachim Strömbergson

2014-03-13	Adding Python program to test the uart.	Joachim Strömbergson

2014-03-13	Adding testbench for the uart.	Joachim Strömbergson

2014-03-13	Adding RTL files for the uart.	Joachim Strömbergson