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AgeCommit message (Expand)Author
2015-12-13whack copyrightsHEADmasterPaul Selkirk
2015-03-31Fix testbench to match new file organization.Paul Selkirk
2015-03-31Don't delay register reads in uart_regs.Paul Selkirk
2015-03-17Rearrange cores.Paul Selkirk
2014-11-07Changed to asynch reset.Joachim Strömbergson
2014-05-09Update of core address size to 8 bits. Changed use of bit rate, data and stop...Joachim Strömbergson
2014-05-09Update of core to use bitrate, data bits and stop bits supplied via ports.Joachim Strömbergson
2014-05-09Adding support for setting bit rate, data- and stop bits.Joachim Strömbergson
2014-03-17Changing from blocking to correct, non-blocking assignments in reg update.Joachim Strömbergson
2014-03-17Adding size constraints to constant definitions to remove synthesis warnings.Joachim Strömbergson
2014-03-13Adding Python program to test the uart.Joachim Strömbergson
2014-03-13Adding testbench for the uart.Joachim Strömbergson
2014-03-13Adding RTL files for the uart.Joachim Strömbergson