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authorJoachim StroĢˆmbergson <joachim@secworks.se>2014-03-17 09:55:01 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2014-03-17 09:55:01 +0100
commit5d15271e9fafb42575caa0dccffa48e68277ee89 (patch)
tree2629b426740f87b03168423cfd645960a154c432 /src
parentb250c13a0dda87d74ef35e8d1fb4f04e0b30949c (diff)
Changing from blocking to correct, non-blocking assignments in reg update.
Diffstat (limited to 'src')
-rw-r--r--src/rtl/uart_core.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/rtl/uart_core.v b/src/rtl/uart_core.v
index 5596958..af2f5a0 100644
--- a/src/rtl/uart_core.v
+++ b/src/rtl/uart_core.v
@@ -216,7 +216,7 @@ module uart_core(
if (rxd_syn_we)
begin
- rxd_syn_reg = rxd_syn_new;
+ rxd_syn_reg <= rxd_syn_new;
end
if (erx_ctrl_we)
@@ -226,12 +226,12 @@ module uart_core(
if (txd_we)
begin
- txd_reg = txd_new;
+ txd_reg <= txd_new;
end
if (txd_byte_we)
begin
- txd_byte_reg = txd_byte_new;
+ txd_byte_reg <= txd_byte_new;
end
if (txd_bit_ctr_we)
@@ -246,7 +246,7 @@ module uart_core(
if (txd_ack_we)
begin
- txd_ack_reg = txd_ack_new;
+ txd_ack_reg <= txd_ack_new;
end
if (etx_ctrl_we)