| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-03-17 | Rearrange cores. | Paul Selkirk |
| 2014-11-07 | Changed to asynch reset. | Joachim Strömbergson |
| 2014-05-09 | Update of core address size to 8 bits. Changed use of bit rate, data and stop... | Joachim Strömbergson |
| 2014-05-09 | Update of core to use bitrate, data bits and stop bits supplied via ports. | Joachim Strömbergson |
| 2014-05-09 | Adding support for setting bit rate, data- and stop bits. | Joachim Strömbergson |
| 2014-03-17 | Changing from blocking to correct, non-blocking assignments in reg update. | Joachim Strömbergson |
| 2014-03-17 | Adding size constraints to constant definitions to remove synthesis warnings. | Joachim Strömbergson |
| 2014-03-13 | Adding Python program to test the uart. | Joachim Strömbergson |
| 2014-03-13 | Adding testbench for the uart. | Joachim Strömbergson |
| 2014-03-13 | Adding RTL files for the uart. | Joachim Strömbergson |
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index : core/comm/uart | |
| A Universal asynchronous receiver/transmitter (UART) implemented in Verilog | git repositories |
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