core/cipher/chacha - Verilog 2001 implementation of the ChaCha stream cipher

Age	Commit message (Collapse)	Author
2019-02-08	(1) Removed reset input port from qr module, qr module instances and qr ↵HEAD master	Joachim Strömbergson
	module tb. (2) Fixed non blocking assigment erroneously used in comboinational process.
2018-08-23	Debugged pipeline register and state update. All test cases ok.timing_fix	Joachim Strömbergson

2018-08-23	Added missing define.	Joachim Strömbergson

2018-08-23	(1) Adding pipeline register update code and a set of pipeline registers. ↵	Joachim Strömbergson
	Registers are not connected at the this stage. (2) Added self testing tetst cases and debug outputs to observe internal behaviour.
2018-08-23	(1) Updated qr interface to include clock and reset needed for internal ↵	Joachim Strömbergson
	pipeline registers. (2) Added testbench for the qr module. (3) Added qr simulation target. (4) Added lint support.
2016-12-28	(1) Cleanup of top an core code with no functional changes. The code is now ↵cleanup	Joachim Strömbergson
	much more compact. (2) Fixed how the QR modules are used in parallel to actually work in parallel. This increases performance. (3) Changed registers into arrays and cleaned up how operands and data are accessed. This decreased total design size.
2015-04-30	(1) Added api addresses and constants for core name and version. (2) Changed ↵	Joachim Strömbergson
	addresses for control, status and config to match the ct standard. (3) Updated the testbench to use the changed addresses.
2014-09-03	Adding testbenches for core and top.	Joachim Strömbergson