core/cipher/chacha - Verilog 2001 implementation of the ChaCha stream cipher

Age	Commit message (Expand)	Author
2019-02-08	(1) Removed reset input port from qr module, qr module instances and qr modul...HEAD master	Joachim Strömbergson
2019-02-07	Change reset to asynch assert. This matches comment. It also matches what is ...	Joachim Strömbergson
2018-08-30	Adding two more pipeline registers in the qr module. Added two more wait cycles.	Joachim Strömbergson
2018-08-23	Debugged pipeline register and state update. All test cases ok.timing_fix	Joachim Strömbergson
2018-08-23	(1) Adding pipeline register update code and a set of pipeline registers. Reg...	Joachim Strömbergson
2018-08-23	(1) Updated qr interface to include clock and reset needed for internal pipel...	Joachim Strömbergson
2014-11-06	Fixes to nits found using the verilator linter.	Joachim Strömbergson
2014-09-03	Adding RTL code for the ChaCha stream cipher.	Joachim Strömbergson