core/cipher/chacha - Verilog 2001 implementation of the ChaCha stream cipher

Age	Commit message (Collapse)	Author
2019-02-08	(1) Removed reset input port from qr module, qr module instances and qr ↵HEAD master	Joachim Strömbergson
	module tb. (2) Fixed non blocking assigment erroneously used in comboinational process.
2019-02-07	Change reset to asynch assert. This matches comment. It also matches what is ↵	Joachim Strömbergson
	used in the TRNG core where the chacha core is instantiated. Also removed reset from the pipeline registers.
2018-08-30	Adding two more pipeline registers in the qr module. Added two more wait cycles.	Joachim Strömbergson

2018-08-23	Debugged pipeline register and state update. All test cases ok.timing_fix	Joachim Strömbergson

2018-08-23	(1) Adding pipeline register update code and a set of pipeline registers. ↵	Joachim Strömbergson
	Registers are not connected at the this stage. (2) Added self testing tetst cases and debug outputs to observe internal behaviour.
2018-08-23	(1) Updated qr interface to include clock and reset needed for internal ↵	Joachim Strömbergson
	pipeline registers. (2) Added testbench for the qr module. (3) Added qr simulation target. (4) Added lint support.
2014-11-06	Fixes to nits found using the verilator linter.	Joachim Strömbergson

2014-09-03	Adding RTL code for the ChaCha stream cipher.	Joachim Strömbergson