Change reset to asynch assert. This matches comment. It also matches what is used in the TRNG core where the chacha core is instantiated. Also removed reset from the pipeline registers.

1 files changed, 1 insertions, 1 deletions

diff --git a/src/rtl/chacha_core.v b/src/rtl/chacha_core.v
index cc91327..20aecec 100644
--- a/src/rtl/chacha_core.v
+++ b/src/rtl/chacha_core.v
@@ -269,7 +269,7 @@ module chacha_core(
   // All registers are positive edge triggered with synchronous
   // active low reset. All registers have write enable.
   //----------------------------------------------------------------
-  always @ (posedge clk)
+  always @ (posedge clk or negedge reset_n)
     begin : reg_update
      integer i;