From de3f38a835ad9ac5ad8b6153a6b363c23641a3f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Thu, 7 Feb 2019 14:30:01 +0100 Subject: Change reset to asynch assert. This matches comment. It also matches what is used in the TRNG core where the chacha core is instantiated. Also removed reset from the pipeline registers. --- src/rtl/chacha_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/rtl/chacha_core.v') diff --git a/src/rtl/chacha_core.v b/src/rtl/chacha_core.v index cc91327..20aecec 100644 --- a/src/rtl/chacha_core.v +++ b/src/rtl/chacha_core.v @@ -269,7 +269,7 @@ module chacha_core( // All registers are positive edge triggered with synchronous // active low reset. All registers have write enable. //---------------------------------------------------------------- - always @ (posedge clk) + always @ (posedge clk or negedge reset_n) begin : reg_update integer i; -- cgit v1.2.3