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| author | Rob Austein <sra@hactrn.net> | 2020-03-22 17:27:24 +0000 |
|---|---|---|
| committer | Rob Austein <sra@hactrn.net> | 2020-03-22 17:27:24 +0000 |
| commit | 6e7acd77707c16aa79cec22238ef944682d9184b (patch) | |
| tree | dbfce74eca04e08a908631a1976194c26702d79b /verilog-integer.py | |
| parent | 34ecad1d04c6b3add8077315bac1f954002fb7da (diff) | |
Python 2 -> 3
Diffstat (limited to 'verilog-integer.py')
| -rw-r--r-- | verilog-integer.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/verilog-integer.py b/verilog-integer.py index 5186f44..f7eee40 100644 --- a/verilog-integer.py +++ b/verilog-integer.py @@ -57,7 +57,7 @@ class VerilogInteger(object): if __name__ == "__main__": def show(*args): - print "{:20} | {:20} | {:20}".format(*args) + print("{:20} | {:20} | {:20}".format(*args)) show("C", "Verilog", "Input") show("-" * 20, "-" * 20, "-" * 20) |