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-rw-r--r--verilog-integer.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/verilog-integer.py b/verilog-integer.py
index 5186f44..f7eee40 100644
--- a/verilog-integer.py
+++ b/verilog-integer.py
@@ -57,7 +57,7 @@ class VerilogInteger(object):
if __name__ == "__main__":
def show(*args):
- print "{:20} | {:20} | {:20}".format(*args)
+ print("{:20} | {:20} | {:20}".format(*args))
show("C", "Verilog", "Input")
show("-" * 20, "-" * 20, "-" * 20)