| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-07-19 | Fixed copyright notices.HEADmaster | Pavel V. Shatov (Meister) | |
| 2020-02-11 | More closely follow how things work in hardware. | Pavel V. Shatov (Meister) | |
| 2020-01-20 | * mostly cosmetic fixes related to debug output | Pavel V. Shatov (Meister) | |
| * fixed REGULAR_ADD opcode to match how hardware works | |||
| 2019-10-17 | Added readme file | Pavel V. Shatov (Meister) | |
| 2019-10-17 | - Switched to default key length of 512 for faster simulation | Pavel V. Shatov (Meister) | |
| - Added an option to dump vectors as C array initializers for easy import into the STM32 sample driver - Added an option to dump entire core memory to assist debugging in hardware - Reading from bank now returns a copy of its contents, not a link - Reworked how carry propagation works (no more in-place overwrites) - Implemented "caching" of bank contents to match how things actually work in hardware (eg. after switching to twice smaller modulus before doing the CRT ladder, the upper half of the larger modulus stays in place) - Optimized microcode - Various cosmetic fixes | |||
| 2019-10-01 | Moved here from "modexpng" repo. | Pavel V. Shatov (Meister) | |
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index : user/shatov/modexpng_fpga_model | |
| Math model of ModExpNG IP core | git repositories |
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