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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-17 21:15:51 +0300 |
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| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-17 21:15:51 +0300 |
| commit | 6fddcde0083d383de06ff9b04c5aed88347ffe31 (patch) | |
| tree | 91a5141b8595e4fdf10573d46070aeed74a7862f | |
| parent | 9a3c126dc09d7e128919886554ec6ce5d1fb88d7 (diff) | |
Added readme file
| -rw-r--r-- | README.md | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/README.md b/README.md new file mode 100644 index 0000000..ddef800 --- /dev/null +++ b/README.md @@ -0,0 +1,6 @@ +modexpng_fpga_model +=================== + +Math model of ModExpNG IP core. The model mimics how an FPGA does modular exponentiation. + +First use the scripts from the `vector/` folder to generate and format a keypair vector, then edit the <i>DUMP_*</i> switches in `modexpng_fpga_model.py` to dump the desired internal values. The <i>FORCE_OVERFLOW</i> setting artificially forces the virtually neven seen internal interim overflow situation and allows its handler to be tested. You can also un-comment the _#c.dump_banks()_ line and move it anywhere within _sign_using_crt()_ and/or _sign_without_crt()_ to dump the contents of entire core's memory. |