| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | Makefile | 763 | logplainblame |
| -rw-r--r-- | README.md | 1051 | logplainblame |
| -rw-r--r-- | modexp_fpga_model.cpp | 10246 | logplainblame |
| -rw-r--r-- | modexp_fpga_model.h | 3370 | logplainblame |
| -rw-r--r-- | modexp_fpga_model_montgomery.cpp | 13453 | logplainblame |
| -rw-r--r-- | modexp_fpga_model_montgomery.h | 2743 | logplainblame |
| -rw-r--r-- | modexp_fpga_model_pe.cpp | 4656 | logplainblame |
| -rw-r--r-- | modexp_fpga_model_pe.h | 2345 | logplainblame |
| d--------- | test | 354 | logplain |
 |
index : user/shatov/modexp_fpga_model | |
| Reference model was written to help debug Verilog code | git repositories |
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