BranchCommit messageAuthorAge
masterMerge branch 'master' of git.cryptech.is:user/shatov/modexp_fpga_modelPavel V. Shatov (Meister)4 years
AgeCommit messageAuthor
2017-08-12Merge branch 'master' of git.cryptech.is:user/shatov/modexp_fpga_modelHEADmasterPavel V. Shatov (Meister)
2017-08-11Renamed some of the test vector components for improved consistency.Pavel V. Shatov (Meister)
2017-08-11Cosmetic changes.Pavel V. Shatov (Meister)
2017-08-10Generate additional quantities required for testing of CRT in hardware.Pavel V. Shatov (Meister)
2017-08-06Follow what Verilog does more closely.Pavel V. Shatov (Meister)
2017-07-18Changes to the model:Pavel V. Shatov (Meister)
2017-07-08Minor update, there's no need to update Aj inside of systolic loop.Pavel V. Shatov (Meister)
2017-07-05Turned systolic multiplication into a separate routine.Pavel V. Shatov (Meister)
2017-07-05Triple multiplier turns out to be an overkill in Verilog, started turningPavel V. Shatov (Meister)
2017-06-29Follow what Verilog does more precisely.Pavel V. Shatov (Meister)