user/shatov/modexp_fpga_model - Reference model was written to help debug Verilog code

Branch	Commit message	Author	Age
master	Merge branch 'master' of git.cryptech.is:user/shatov/modexp_fpga_model	Pavel V. Shatov (Meister)	7 years


Age	Commit message	Author
2017-08-12	Merge branch 'master' of git.cryptech.is:user/shatov/modexp_fpga_modelHEAD master	Pavel V. Shatov (Meister)
2017-08-11	Renamed some of the test vector components for improved consistency.	Pavel V. Shatov (Meister)
2017-08-11	Cosmetic changes.	Pavel V. Shatov (Meister)
2017-08-10	Generate additional quantities required for testing of CRT in hardware.	Pavel V. Shatov (Meister)
2017-08-06	Follow what Verilog does more closely.	Pavel V. Shatov (Meister)
2017-07-18	Changes to the model:	Pavel V. Shatov (Meister)
2017-07-08	Minor update, there's no need to update Aj inside of systolic loop.	Pavel V. Shatov (Meister)
2017-07-05	Turned systolic multiplication into a separate routine.	Pavel V. Shatov (Meister)
2017-07-05	Triple multiplier turns out to be an overkill in Verilog, started turning	Pavel V. Shatov (Meister)
2017-06-29	Follow what Verilog does more precisely.	Pavel V. Shatov (Meister)
[...]

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