| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-08-06 | Follow what Verilog does more closely. | Pavel V. Shatov (Meister) |
| 2017-07-18 | Changes to the model: | Pavel V. Shatov (Meister) |
| 2017-07-05 | Turned systolic multiplication into a separate routine. | Pavel V. Shatov (Meister) |
| 2017-07-05 | Triple multiplier turns out to be an overkill in Verilog, started turning | Pavel V. Shatov (Meister) |
| 2017-06-29 | Follow what Verilog does more precisely. | Pavel V. Shatov (Meister) |
| 2017-06-24 | Improved the model: | Pavel V. Shatov (Meister) |
| 2017-06-13 | Initial commit of faster modular exponentiation model based on systolic archi... | Pavel V. Shatov (Meister) |
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index : user/shatov/modexp_fpga_model | |
| Reference model was written to help debug Verilog code | git repositories |
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