diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-06-13 20:11:58 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-06-13 20:11:58 +0300 |
| commit | 53e92c5355aca120eab8d59e6904282c9e3b4ab1 (patch) | |
| tree | 62c6b65e52c01bbbfdac063ec8ba791a9d073203 /modexp_fpga_model.h | |
Initial commit of faster modular exponentiation model based on systolic architecture.
Diffstat (limited to 'modexp_fpga_model.h')
| -rw-r--r-- | modexp_fpga_model.h | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/modexp_fpga_model.h b/modexp_fpga_model.h new file mode 100644 index 0000000..2a91d32 --- /dev/null +++ b/modexp_fpga_model.h @@ -0,0 +1,77 @@ +//
+// modexp_fpga_model.h
+// -----------------------------------------------
+// Model of fast modular exponentiation on an FPGA
+//
+// Authors: Pavel Shatov
+// Copyright (c) 2017, NORDUnet A/S
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+
+
+//----------------------------------------------------------------
+// Headers
+//----------------------------------------------------------------
+#include <stdint.h> // uintNN_t
+#include <stddef.h> // size_t
+#include <limits.h> // CHAR_BIT
+
+
+//----------------------------------------------------------------
+// Data types
+//----------------------------------------------------------------
+typedef uint32_t FPGA_WORD; // FPGA data bus width
+typedef uint64_t _WIDE_WORD; // only used internally to mimic DSP slice operation
+
+
+//----------------------------------------------------------------
+// Model settings
+//----------------------------------------------------------------
+#define MAX_OPERAND_WIDTH 512 // largest supported operand width in bits
+#define SYSTOLIC_WIDTH 128 // width of systolic array in bits
+
+
+//----------------------------------------------------------------
+// Handy values
+//----------------------------------------------------------------
+
+ // largest possible number of 32-bit words in an operand
+#define MAX_OPERAND_WORDS (MAX_OPERAND_WIDTH / (CHAR_BIT * sizeof(FPGA_WORD)))
+
+ // number of words systolic array processes at once
+#define SYSTOLIC_NUM_WORDS (SYSTOLIC_WIDTH / (CHAR_BIT * sizeof(FPGA_WORD)))
+
+ // largest possible number of consequtive systolic cycles
+ // that are necessary to process entire operand
+#define MAX_SYSTOLIC_CYCLES (MAX_OPERAND_WIDTH / SYSTOLIC_WIDTH)
+
+
+//----------------------------------------------------------------
+// End of file
+//----------------------------------------------------------------
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