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path: root/ecdsa_fpga_microcode.h
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2021-07-19Fixed copyright notices.Pavel V. Shatov (Meister)
2021-04-11Forgot to add copyright yearPavel V. Shatov (Meister)
2021-04-11 * Microcode layer redesigned to take advantage of Montgomery ladderPavel V. Shatov (Meister)
architecture. Instead of R and S there are now two working ("cycle") registers R0 and R1. After every cycle R0+R1 is placed in register S ("sum"), 2*R0|1 (depending on current multiplier bit) is placed in register T. Then the working variables are updated, final result ends up in R0. * Due to the change of working registers, modular inversion routines were updated accordingly. * Added optional debugging output control
2018-12-19 * New hardware architecturePavel V. Shatov (Meister)
* Randomized test vector