* New hardware architecture

 * Randomized test vector

1 files changed, 164 insertions, 0 deletions

diff --git a/ecdsa_fpga_microcode.h b/ecdsa_fpga_microcode.h
new file mode 100644
index 0000000..f551d96
--- /dev/null
+++ b/ecdsa_fpga_microcode.h
@@ -0,0 +1,164 @@
+//------------------------------------------------------------------------------
+//
+// ecdsa_fpga_microcode.h
+// --------------------------------
+// Microcode Architecture for ECDSA
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2018 NORDUnet A/S
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// - Redistributions of source code must retain the above copyright notice,
+//   this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright notice,
+//   this list of conditions and the following disclaimer in the documentation
+//   and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may be
+//   used to endorse or promote products derived from this software without
+//   specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+#include <stdlib.h>	// NULL
+
+
+//------------------------------------------------------------------------------
+enum UOP_BANK
+//------------------------------------------------------------------------------
+{
+	BANK_LO, BANK_HI
+};
+
+//--------------------------
+enum UOP_OPERAND
+//--------------------------
+{
+	CONST_ZERO,     //  0
+	CONST_ONE,      //  1
+    CONST_DELTA,    //  2
+
+	CONST_GX,       //  3
+	CONST_GY,       //  4
+    
+	CONST_HX,       //  5
+	CONST_HY,       //  6
+
+	CYCLE_RX,       //  7
+	CYCLE_RY,       //  8
+	CYCLE_RZ,       //  9
+
+	CYCLE_SX,       // 10
+	CYCLE_SY,       // 11
+	CYCLE_SZ,       // 12
+
+    CYCLE_A,        // 13
+    CYCLE_A2,       // 14
+    CYCLE_B,        // 15
+    CYCLE_C,        // 16
+    CYCLE_C2,       // 17
+    CYCLE_C2_2,     // 18
+    CYCLE_D,        // 19
+    CYCLE_E,        // 20
+    CYCLE_F,        // 21
+    CYCLE_G,        // 22
+    CYCLE_H,        // 23
+    CYCLE_J,        // 24
+
+    CYCLE_Z2,       // 25
+
+    CYCLE_T1,       // 26
+    CYCLE_T2,       // 27
+    CYCLE_T3,       // 28
+    CYCLE_T4,       // 29
+
+	INVERT_R1,      // 30
+    INVERT_R2,      // 31
+
+	INVERT_X2,      // 32
+	INVERT_X3,      // 33
+	INVERT_X6,      // 34
+	INVERT_X12,     // 35
+	INVERT_X15,     // 36
+	INVERT_X30,     // 37
+    INVERT_X32,     // 38
+    INVERT_X60,     // 39
+	INVERT_X120,    // 40
+
+	INVERT_A2,      // 41
+    INVERT_A3,      // 42
+
+	ECDSA_UOP_OPERAND_COUNT
+};
+
+//------------------------------------------------------------------------------
+enum UOP_MATH
+//------------------------------------------------------------------------------
+{
+	ADD, SUB, MUL
+};
+
+
+//------------------------------------------------------------------------------
+// Global Storage Buffers
+//------------------------------------------------------------------------------
+extern FPGA_BUFFER BUF_LO[ECDSA_UOP_OPERAND_COUNT];
+extern FPGA_BUFFER BUF_HI[ECDSA_UOP_OPERAND_COUNT];
+
+
+//------------------------------------------------------------------------------
+// Global Flags
+//------------------------------------------------------------------------------
+extern bool uop_flagz_sz;
+extern bool uop_flagz_rz;
+extern bool uop_flagz_e;
+extern bool uop_flagz_f;
+
+
+//------------------------------------------------------------------------------
+// Loop Macros
+//------------------------------------------------------------------------------
+#define uop_loop                int uop_cnt
+#define uop_cycle(iters);		for (uop_cnt=0; uop_cnt<iters; uop_cnt++) {
+#define uop_repeat();			}
+#define uop_calc_if_even(...)	if (!(uop_cnt % 2)) uop_calc(__VA_ARGS__)
+#define uop_calc_if_odd(...)	else uop_calc(__VA_ARGS__)
+
+
+//------------------------------------------------------------------------------
+// Prototypes (Micro-Operations)
+//------------------------------------------------------------------------------
+void uop_move(enum UOP_BANK src, int s_op1, UOP_BANK dst, int d_op1);
+void uop_cmpz(UOP_BANK src, int s_op);
+
+void uop_calc (UOP_MATH math,
+               UOP_BANK src, int s_op1, int s_op2,
+               UOP_BANK dst, int d_op);
+
+void uop_load(const FPGA_BUFFER *mem, UOP_BANK dst, int d_op);
+void uop_stor(UOP_BANK src, int s_op, FPGA_BUFFER *mem);
+
+
+//------------------------------------------------------------------------------
+// End-of-File
+//------------------------------------------------------------------------------