| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-07-19 | Fixed copyright notices. | Pavel V. Shatov (Meister) | |
| 2021-04-11 | Forgot to add copyright year | Pavel V. Shatov (Meister) | |
| 2021-04-11 | * Microcode layer redesigned to take advantage of Montgomery ladder | Pavel V. Shatov (Meister) | |
| architecture. Instead of R and S there are now two working ("cycle") registers R0 and R1. After every cycle R0+R1 is placed in register S ("sum"), 2*R0|1 (depending on current multiplier bit) is placed in register T. Then the working variables are updated, final result ends up in R0. * Due to the change of working registers, modular inversion routines were updated accordingly. * Added optional debugging output control | |||
| 2018-12-19 | * New hardware architecture | Pavel V. Shatov (Meister) | |
| * Randomized test vector | |||
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index : user/shatov/ecdsa_fpga_model | |
| Reference model written to help debug Verilog code | git repositories |
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path: root/ecdsa_fpga_microcode.h