user/shatov/curve25519_fpga_model - Reference model written to help debug Verilog code

Age	Commit message (Collapse)	Author
2018-10-15	Ed25519 microcode parser. Verilog Ed25519 core is microsequenced, it contains a	Pavel V. Shatov (Meister)
	"worker" module that fetches opcodes from a piece of read-only memory and does either "move" (copy) or "math" (add/subtract/multiply) operation. The C model mimics how this worker unit operates by calling routines that correspond to micro-operations. This parser processes the C model sources and generates a piece of Verilog that is used to initialize the microcode ROM.