| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-12-19 | Tiny cleanup.HEADmaster | Pavel V. Shatov (Meister) | |
| 2018-11-09 | Added randomized test vector. | Pavel V. Shatov (Meister) | |
| 2018-10-15 | Ed25519 microcode parser. Verilog Ed25519 core is microsequenced, it contains a | Pavel V. Shatov (Meister) | |
| "worker" module that fetches opcodes from a piece of read-only memory and does either "move" (copy) or "math" (add/subtract/multiply) operation. The C model mimics how this worker unit operates by calling routines that correspond to micro-operations. This parser processes the C model sources and generates a piece of Verilog that is used to initialize the microcode ROM. | |||
| 2018-10-15 | Reworked Ed25519-specific microcode, added magic markers to allow automatic | Pavel V. Shatov (Meister) | |
| parsing. | |||
| 2018-09-24 | Ed25519 tester | Pavel V. Shatov (Meister) | |
| 2018-09-24 | Ed25519-specific code (curve base point multiplication) | Pavel V. Shatov (Meister) | |
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index : user/shatov/curve25519_fpga_model | |
| Reference model written to help debug Verilog code | git repositories |
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