diff options
Diffstat (limited to 'rtl/src/verilog/core_selector.v')
| -rw-r--r-- | rtl/src/verilog/core_selector.v | 44 |
1 files changed, 43 insertions, 1 deletions
diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v index 8ce2003..092a704 100644 --- a/rtl/src/verilog/core_selector.v +++ b/rtl/src/verilog/core_selector.v @@ -3,9 +3,12 @@ // core_selector.v // --------------- // Core selector Cryptech Novena FPGA framework. +// This is basically the top of the Cryptech subsystem for the +// FPGA. The module is responsible for selecting which core is +// connected to the extermal high speed interface. // // -// Author: Pavel Shatov +// Author: Pavel Shatov, Paul Sekirk, Joachim Strömbergson // Copyright (c) 2014, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -41,9 +44,13 @@ module core_selector input wire sys_clk, input wire sys_rst, + input wire ct_noise, + output wire [07 : 0] ct_led, + input wire [13: 0] sys_eim_addr, input wire sys_eim_wr, input wire sys_eim_rd, + output wire [31 : 0] read_data, input wire [31 : 0] write_data ); @@ -136,6 +143,41 @@ module core_selector ); + //---------------------------------------------------------------- + // Cryptech Logic + // + // Logic specific to the Cryptech use of the Novena. + // Currently we just sample the noise and drive the LEDs + // with this signal. + //---------------------------------------------------------------- + reg ct_noise_sample0_reg; + reg ct_noise_sample1_reg; + reg [7 : 0] ct_led_reg; + + always @ (posedge sys_clk) + begin + if (sys_rst) + begin + ct_led_reg <= 8'h00; + ct_noise_sample0_reg <= 1'b0; + ct_noise_sample1_reg <= 1'b0; + end + else + begin + ct_noise_sample0_reg <= ct_noise; + ct_noise_sample1_reg <= ct_noise_sample0_reg; + ct_led_reg[0] <= ct_noise_sample1_reg; + ct_led_reg[1] <= ct_noise_sample1_reg; + ct_led_reg[2] <= ct_noise_sample1_reg; + ct_led_reg[3] <= ct_noise_sample1_reg; + ct_led_reg[4] <= ct_noise_sample1_reg; + ct_led_reg[5] <= ct_noise_sample1_reg; + ct_led_reg[6] <= ct_noise_sample1_reg; + ct_led_reg[7] <= ct_noise_sample1_reg; + end + end + + assign ct_led = ct_led_reg; endmodule |