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authorJoachim StroĢˆmbergson <joachim@secworks.se>2015-02-01 09:03:37 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2015-02-01 09:03:37 +0100
commit5150947e0bfc393b03e49bcb37e1168eb02f5b67 (patch)
treee800d87f2142c31fece7c15b1e26b368b670c624 /rtl/src/ipcore/_xmsgs
parent0d258b832847ca29bcf47f1904b7cc4a76e2a191 (diff)
Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.
Diffstat (limited to 'rtl/src/ipcore/_xmsgs')
-rw-r--r--rtl/src/ipcore/_xmsgs/pn_parser.xmsgs2
1 files changed, 1 insertions, 1 deletions
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
index 2ccce38..8fe7625 100644
--- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
+++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/__DNSSEC/novena_baseline/src/ipcore/clkmgr_dcm.v&quot; into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Sandbox/external/cryptech/test/novena_base/rtl/src/ipcore/tmp/_cg/clkmgr_dcm.v&quot; into library work</arg>
</msg>
</messages>