From 5150947e0bfc393b03e49bcb37e1168eb02f5b67 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Sun, 1 Feb 2015 09:03:37 +0100
Subject: Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project
 files.

---
 rtl/src/ipcore/_xmsgs/pn_parser.xmsgs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'rtl/src/ipcore/_xmsgs')

diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
index 2ccce38..8fe7625 100644
--- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
+++ b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
@@ -8,7 +8,7 @@
 <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
 
 <messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/__DNSSEC/novena_baseline/src/ipcore/clkmgr_dcm.v&quot; into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;Z:/Sandbox/external/cryptech/test/novena_base/rtl/src/ipcore/tmp/_cg/clkmgr_dcm.v&quot; into library work</arg>
 </msg>
 
 </messages>
-- 
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