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authorPaul Selkirk <paul@psgd.org>2015-02-10 13:51:40 -0500
committerPaul Selkirk <paul@psgd.org>2015-02-10 13:51:40 -0500
commit0e4e0b5d71b15e1f4edf31295fc95d45d4ae3890 (patch)
tree66d95e0c6d61801a1f72de5b8f8af89a5b9d85cd /rtl/src/ipcore/_xmsgs
parent560ebacb0c576b92d7b64d728423683ad974885e (diff)
First stage of integration cleanup.
Add local SHA core wrappers, due to the need for registered outputs. Remove unused demo-adder code, and reorganize sw directory.
Diffstat (limited to 'rtl/src/ipcore/_xmsgs')
-rw-r--r--rtl/src/ipcore/_xmsgs/pn_parser.xmsgs15
1 files changed, 0 insertions, 15 deletions
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index 04083bd..0000000
--- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated -->
-<!-- by the Xilinx ISE software. Any direct editing or -->
-<!-- changes made to this file may result in unpredictable -->
-<!-- behavior or data corruption. It is strongly advised that -->
-<!-- users do not edit the contents of this file. -->
-<!-- -->
-<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
-
-<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/__DNSSEC/novena_base/rtl/src/ipcore/clkmgr_dcm.v&quot; into library work</arg>
-</msg>
-
-</messages>
-