aboutsummaryrefslogtreecommitdiff
path: root/rtl/src/ipcore
diff options
context:
space:
mode:
authorPaul Selkirk <paul@psgd.org>2015-02-10 13:51:40 -0500
committerPaul Selkirk <paul@psgd.org>2015-02-10 13:51:40 -0500
commit0e4e0b5d71b15e1f4edf31295fc95d45d4ae3890 (patch)
tree66d95e0c6d61801a1f72de5b8f8af89a5b9d85cd /rtl/src/ipcore
parent560ebacb0c576b92d7b64d728423683ad974885e (diff)
First stage of integration cleanup.
Add local SHA core wrappers, due to the need for registered outputs. Remove unused demo-adder code, and reorganize sw directory.
Diffstat (limited to 'rtl/src/ipcore')
-rw-r--r--rtl/src/ipcore/_xmsgs/pn_parser.xmsgs15
-rw-r--r--rtl/src/ipcore/clkmgr_dcm.gise25
-rw-r--r--rtl/src/ipcore/clkmgr_dcm.ncf120
-rw-r--r--rtl/src/ipcore/clkmgr_dcm.xise4
4 files changed, 85 insertions, 79 deletions
diff --git a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs b/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index 04083bd..0000000
--- a/rtl/src/ipcore/_xmsgs/pn_parser.xmsgs
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated -->
-<!-- by the Xilinx ISE software. Any direct editing or -->
-<!-- changes made to this file may result in unpredictable -->
-<!-- behavior or data corruption. It is strongly advised that -->
-<!-- users do not edit the contents of this file. -->
-<!-- -->
-<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
-
-<messages>
-<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/__DNSSEC/novena_base/rtl/src/ipcore/clkmgr_dcm.v&quot; into library work</arg>
-</msg>
-
-</messages>
-
diff --git a/rtl/src/ipcore/clkmgr_dcm.gise b/rtl/src/ipcore/clkmgr_dcm.gise
index 31ed488..4cfaf34 100644
--- a/rtl/src/ipcore/clkmgr_dcm.gise
+++ b/rtl/src/ipcore/clkmgr_dcm.gise
@@ -15,7 +15,7 @@
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
@@ -26,6 +26,27 @@
<file xil_pn:fileType="FILE_VEO" xil_pn:name="clkmgr_dcm.veo" xil_pn:origination="imported"/>
</files>
- <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2136445705273696504" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5299826667237415001" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1423590634" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2601148782814295670" xil_pn:start_ts="1423590634">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ </transforms>
</generated_project>
diff --git a/rtl/src/ipcore/clkmgr_dcm.ncf b/rtl/src/ipcore/clkmgr_dcm.ncf
index 0e5eb73..ef4e259 100644
--- a/rtl/src/ipcore/clkmgr_dcm.ncf
+++ b/rtl/src/ipcore/clkmgr_dcm.ncf
@@ -1,60 +1,60 @@
-# file: clkmgr_dcm.ucf
-#
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-#
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-#
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-#
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-#
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-#
-
-# Input clock periods. These duplicate the values entered for the
-# input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
-
-
-# FALSE PATH constraints
-PIN "RESET" TIG;
-
-
+# file: clkmgr_dcm.ucf
+#
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.0 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints
+PIN "RESET" TIG;
+
+
diff --git a/rtl/src/ipcore/clkmgr_dcm.xise b/rtl/src/ipcore/clkmgr_dcm.xise
index a0ba9da..7369d3b 100644
--- a/rtl/src/ipcore/clkmgr_dcm.xise
+++ b/rtl/src/ipcore/clkmgr_dcm.xise
@@ -9,10 +9,10 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="clkmgr_dcm.ucf" xil_pn:type="FILE_UCF">