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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2015-01-31 09:03:06 +0100 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2015-01-31 09:03:06 +0100 |
| commit | a68ffdd6c327bcc5d0c0524c4dacd6ceeaf839d7 (patch) | |
| tree | 2fc4876ab32718ce45943e960fbd1f8be16eb1d5 /rtl/src/ipcore/_xmsgs/cg.xmsgs | |
| parent | 785767f35cdee9aca04969b97734e05351bb084d (diff) | |
Adding all main hw source files and constraints.
Diffstat (limited to 'rtl/src/ipcore/_xmsgs/cg.xmsgs')
| -rw-r--r-- | rtl/src/ipcore/_xmsgs/cg.xmsgs | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/rtl/src/ipcore/_xmsgs/cg.xmsgs b/rtl/src/ipcore/_xmsgs/cg.xmsgs new file mode 100644 index 0000000..985e6e3 --- /dev/null +++ b/rtl/src/ipcore/_xmsgs/cg.xmsgs @@ -0,0 +1,27 @@ +<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages> +<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'clkmgr_dcm' already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+ +<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis</arg>
+</msg>
+ +<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+ +<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+ +</messages> +
|