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2018-12-07Adding API support for key loaded status and key timeout control. Added ports...Joachim Strömbergson
2018-09-11Adding a huge, self testing test case.Joachim Strömbergson
2018-09-07Updated testbench to use the new API. Verified that the new API works. No mor...Joachim Strömbergson
2018-09-07Removed r_bank from dump since it no longer exists.Joachim Strömbergson
2018-09-07Test write to all positions in the mem.Joachim Strömbergson
2018-09-04Updated rtl and tb to support parameterized memory size.Joachim Strömbergson
2018-09-04Updated testbench to handle parameterized core.Joachim Strömbergson
2018-09-04Updated testbench to work with the parameterized memory.Joachim Strömbergson
2018-08-24We probably want to be able to read data too.Joachim Strömbergson
2018-08-24Killed the bank switching.Joachim Strömbergson
2018-08-24Performed Verilog parameter magic to make the design scaleable in terms of ca...Joachim Strömbergson
2018-08-23Adding top level defines for setting size and address bits.Joachim Strömbergson
2018-08-16Adding delay cycle to API regs to match the latency for accessing the blockRA...Joachim Strömbergson
2018-08-16Updated the info about max object size supports and number of banks.Joachim Strömbergson
2018-08-15Fix some misleading messages, and enable all tests.Paul Selkirk
2018-07-24Added explicit width specification for constant to silence truncation warning.Joachim Strömbergson
2018-07-06Updated README with status and information about the implementation.Joachim Strömbergson
2018-07-06(1) Updated version to reflect status. (2) Minor fix after running sim in Mod...Joachim Strömbergson
2018-07-06Adding test case for 4096 bit unwrap. Testcase passed! We have unwrap.Joachim Strömbergson
2018-07-06Debugged key unwrap. First testcase for unwerap passed. Added some more debug...Joachim Strömbergson
2018-07-06(1) Fixed dump of core_addr in testbench to actually show the core_addr. Fixe...Joachim Strömbergson
2018-07-05Adding wait state to allow access from memory to complete. Should be possible...Joachim Strömbergson
2018-07-05Fixing block counter init bug. Enabling detailed debugging. Fixing minor nits.Joachim Strömbergson
2018-07-05Fixed minor details in unwrap test case. Enabled unwrap test case.Joachim Strömbergson
2018-07-05Updated keywrap logic to support unwrap. Split state to handle next start in ...Joachim Strömbergson
2018-07-05Adding state and counter functionality to support unwrap. Changed name of def...Joachim Strömbergson
2018-07-05Adding unwrap test case.Joachim Strömbergson
2018-07-05Adding wrap test case with 4096 bit plaintext from NIST. Test result matches ...Joachim Strömbergson
2018-07-05Removed a few states and a few cycles.Joachim Strömbergson
2018-07-05We use the aes_speed core instead.Joachim Strömbergson
2018-07-05Adding tool to generate write commands.Joachim Strömbergson
2018-07-05Adding testcase for wrapping 4096 bit data.Joachim Strömbergson
2018-07-05We haz keywrap! Time to add more testcases and make them self testing. Oh and...Joachim Strömbergson
2018-07-05Debugged keywrap processing including A update. All AES operations works corr...Joachim Strömbergson
2018-07-05Fixed memory word order. Fixed a number of bugs. First block encrypted correc...Joachim Strömbergson
2018-07-05Removed the streaming interface in favor of a normal address based interface....Joachim Strömbergson
2018-07-03Adding more dump outputs. wrap does not yet work, but one can see when things...Joachim Strömbergson
2018-07-03Good news: The core peformcs all AES operations and stops after correct numbe...Joachim Strömbergson
2018-07-03Debugged a lot of minor errors and added a lot of debug functions. Things are...Joachim Strömbergson
2018-07-03Add support to dump contents of memory to check that data has been written co...Joachim Strömbergson
2018-07-03Added test case with vectors from NIST KWP AE. Test fails. But at least it do...Joachim Strömbergson
2018-07-03Adding a lot of verbose output to get the internal values we need.Joachim Strömbergson
2018-07-03Focusing on a single NIST KWP test case that is non-trivial.Joachim Strömbergson
2018-07-03Adding additional test code to verify that core read-modify-write and api rre...Joachim Strömbergson
2018-07-03Added first tasks to test api write and core read. Everything works as expected.Joachim Strömbergson
2018-07-01Connected the dut in the core testbench.Joachim Strömbergson
2018-06-29Connected the keymem dut into the testbench.Joachim Strömbergson
2018-06-29Adding more tasks for tb infrastructure.Joachim Strömbergson
2018-06-29Adding dut to top level testbench. Adding API definitions. Adding tasks to re...Joachim Strömbergson
2018-06-29Updated status for the core. Getting there.Joachim Strömbergson