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-rw-r--r--src/rtl/keywrap.v33
-rw-r--r--src/rtl/keywrap_core.v3
-rw-r--r--src/tb/tb_keywrap_core.v5
3 files changed, 37 insertions, 4 deletions
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index f8fcbd7..023ed14 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -73,14 +73,17 @@ module keywrap #(parameter ADDR_BITS = 13)
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
- localparam ADDR_STATUS = 8'h09;
- localparam STATUS_READY_BIT = 0;
- localparam STATUS_VALID_BIT = 1;
+ localparam ADDR_STATUS = 8'h09;
+ localparam STATUS_READY_BIT = 0;
+ localparam STATUS_VALID_BIT = 1;
+ localparam STATUS_LOADED_BIT = 2;
localparam ADDR_CONFIG = 8'h0a;
localparam CTRL_ENCDEC_BIT = 0;
localparam CTRL_KEYLEN_BIT = 1;
+ localparam ADDR_TIMEOUT = 8'h0b;
+
localparam ADDR_RLEN = 8'h0c;
localparam ADDR_A0 = 8'h0e;
localparam ADDR_A1 = 8'h0f;
@@ -102,6 +105,8 @@ module keywrap #(parameter ADDR_BITS = 13)
localparam RLEN_BITS = ADDR_BITS - 2;
localparam PAD = ADDR_BITS - 8;
+ localparam DEFAULT_TIMEOUT = 32'hffff0000;
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
@@ -128,11 +133,15 @@ module keywrap #(parameter ADDR_BITS = 13)
reg [31 : 0] key_reg [0 : 7];
reg key_we;
+ reg [31 : 0] timeout_reg;
+ reg timeout_we;
+
reg [31 : 0] api_rd_delay_reg;
reg [31 : 0] api_rd_delay_new;
reg valid_reg;
reg ready_reg;
+ reg loaded_reg;
//----------------------------------------------------------------
@@ -145,6 +154,7 @@ module keywrap #(parameter ADDR_BITS = 13)
wire [(MEM_BITS - 1) : 0] core_api_addr;
wire core_ready;
wire core_valid;
+ wire core_loaded;
wire [255 : 0] core_key;
wire [63 : 0] core_a_init;
wire [63 : 0] core_a_result;
@@ -179,6 +189,9 @@ module keywrap #(parameter ADDR_BITS = 13)
.ready(core_ready),
.valid(core_valid),
+ .loaded(core_loaded),
+
+ .timeout(timeout_reg),
.rlen(rlen_reg),
@@ -214,14 +227,17 @@ module keywrap #(parameter ADDR_BITS = 13)
rlen_reg <= {RLEN_BITS{1'h0}};
valid_reg <= 1'h0;
ready_reg <= 1'h0;
+ loaded_reg <= 1'h0;
a0_reg <= 32'h0;
a1_reg <= 32'h0;
api_rd_delay_reg <= 32'h0;
+ timeout_reg <= DEFAULT_TIMEOUT;
end
else
begin
ready_reg <= core_ready;
valid_reg <= core_valid;
+ loaded_reg <= core_loaded;
init_reg <= init_new;
next_reg <= next_new;
api_rd_delay_reg <= api_rd_delay_new;
@@ -243,6 +259,9 @@ module keywrap #(parameter ADDR_BITS = 13)
if (key_we)
key_reg[address[2 : 0]] <= write_data;
+
+ if (timeout_we)
+ timeout_reg <= write_data;
end
end // reg_update
@@ -285,6 +304,9 @@ module keywrap #(parameter ADDR_BITS = 13)
if (address == {{PAD{1'h0}}, ADDR_CONFIG})
config_we = 1'h1;
+ if (address == {{PAD{1'h0}}, ADDR_TIMEOUT})
+ timeout_we = 1'h1;
+
if (address == {{PAD{1'h0}}, ADDR_RLEN})
rlen_we = 1'h1;
@@ -317,7 +339,10 @@ module keywrap #(parameter ADDR_BITS = 13)
api_rd_delay_new = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg};
if (address == {{PAD{1'h0}}, ADDR_STATUS})
- api_rd_delay_new = {30'h0, valid_reg, ready_reg};
+ api_rd_delay_new = {29'h0, loaded_reg, valid_reg, ready_reg};
+
+ if (address == {{PAD{1'h0}}, ADDR_TIMEOUT})
+ api_rd_delay_new = timeout_reg;
if (address == {{PAD{1'h0}}, ADDR_RLEN})
api_rd_delay_new = {19'h0, rlen_reg};
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index d1e63b0..b16e05d 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -51,6 +51,9 @@ module keywrap_core #(parameter MEM_BITS = 11)
output wire ready,
output wire valid,
+ output wire loaded,
+
+ input wire [31 : 0] timeout,
input wire [(MEM_BITS - 2) : 0] rlen,
diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v
index 17c8f30..1212ad7 100644
--- a/src/tb/tb_keywrap_core.v
+++ b/src/tb/tb_keywrap_core.v
@@ -67,6 +67,8 @@ module tb_keywrap_core();
reg tb_encdec;
wire tb_ready;
wire tb_valid;
+ wire tb_loaded;
+ reg [31 : 0] tb_timeout;
reg [(RLEN_BITS - 1) : 0] tb_rlen;
reg [255 : 0] tb_key;
reg tb_keylen;
@@ -92,6 +94,9 @@ module tb_keywrap_core();
.ready(tb_ready),
.valid(tb_valid),
+ .loaded(tb_loaded),
+
+ .timeout(tb_timeout),
.rlen(tb_rlen),
.key(tb_key),