Connected the dut in the core testbench.

1 files changed, 65 insertions, 5 deletions

diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v
index 875240c..1b9d96a 100644
--- a/src/tb/tb_keywrap_core.v
+++ b/src/tb/tb_keywrap_core.v
@@ -39,13 +39,61 @@
 
 module tb_keywrap_core();
 
+  //----------------------------------------------------------------
+  // Parameters.
+  //----------------------------------------------------------------
   parameter CLK_HALF_PERIOD = 1;
   parameter CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
 
+
+  //----------------------------------------------------------------
+  // Variables, regs and wires.
+  //----------------------------------------------------------------
   integer cycle_ctr;
-  reg tb_sys_clk;
+
+  reg tb_clk;
   reg tb_reset_n;
 
+  reg           tb_init;
+  reg           tb_next;
+  reg           tb_encdec;
+  wire          tb_ready;
+  wire          tb_valid;
+  reg [12 : 0]  tb_rlen;
+  reg [255 : 0] tb_key;
+  reg           tb_keylen;
+  reg  [63 : 0] tb_a_init;
+  wire [63 : 0] tb_a_result;
+  reg           tb_api_cs;
+  reg           tb_api_we;
+  reg [31 : 0]  tb_api_wr_data;
+  wire [31 : 0] tb_api_rd_data;
+
+
+  //----------------------------------------------------------------
+  // Device Under Test.
+  //----------------------------------------------------------------
+  keywrap_core dut(
+                   .clk(tb_clk),
+                   .reset_n(tb_reset_n),
+                   .init(tb_init),
+                   .next(tb_next),
+                   .encdec(tb_encdec),
+                   .ready(tb_ready),
+                   .valid(tb_valid),
+                   .rlen(tb_rlen),
+                   .key(tb_key),
+                   .keylen(tb_keylen),
+                   .a_init(tb_a_init),
+                   .a_result(tb_a_result),
+                   .api_cs(tb_api_cs),
+                   .api_we(tb_api_we),
+                   .api_wr_data(tb_api_wr_data),
+                   .api_rd_data(tb_api_rd_data)
+                  );
+
+
+
 
   //----------------------------------------------------------------
   // clk_gen
@@ -55,7 +103,7 @@ module tb_keywrap_core();
   always
     begin : clk_gen
       #CLK_HALF_PERIOD;
-      tb_sys_clk = !tb_sys_clk;
+      tb_clk = !tb_clk;
     end // clk_gen
 
 
@@ -81,9 +129,21 @@ module tb_keywrap_core();
   //----------------------------------------------------------------
   initial
     begin
-      cycle_ctr     = 0;
-      tb_sys_clk    = 0;
-      tb_reset_n    = 0;
+      cycle_ctr  = 0;
+      tb_clk     = 0;
+      tb_reset_n = 0;
+
+      tb_init        = 0;
+      tb_next        = 0;
+      tb_encdec      = 0;
+      tb_rlen        = 13'h0;
+      tb_key         = 256'h0;
+      tb_keylen      = 0;
+      tb_a_init      = 64'h0;
+      tb_api_cs      = 0;
+      tb_api_we      = 0;
+      tb_api_wr_data = 32'h0;
+
 
       #(CLK_PERIOD * 10);