Completed syntax debug after integration of new mkmif_core wrapper.

3 files changed, 66 insertions, 133 deletions

diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 533cc83..cf6e00a 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -55,6 +55,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
                      input wire                       read,
                      input wire                       write,
                      input wire                       mkey_mstatus,
+                     input wire                       mkey_key,
                      input wire                       encdec,
 
                      output wire                      ready,
@@ -82,43 +83,19 @@ module keywrap_core #(parameter MEM_BITS = 11)
   //----------------------------------------------------------------
   localparam MAX_ITERATIONS = 6 - 1;
 
-  localparam CTRL_IDLE           = 6'h0;
-  localparam CTRL_INIT_WAIT      = 6'h1;
-  localparam CTRL_NEXT_WSTART    = 6'h2;
-  localparam CTRL_NEXT_USTART    = 6'h3;
-  localparam CTRL_NEXT_LOOP0     = 6'h4;
-  localparam CTRL_NEXT_LOOP      = 6'h5;
-  localparam CTRL_NEXT_WAIT      = 6'h6;
-  localparam CTRL_NEXT_UPDATE    = 6'h7;
-  localparam CTRL_NEXT_WCHECK    = 6'h8;
-  localparam CTRL_NEXT_UCHECK    = 6'h9;
-  localparam CTRL_NEXT_FINALIZE  = 6'ha;
-
-  localparam CTRL_MKM_RD_START   = 6'h10;
-  localparam CTRL_MKM_RD_WAIT0   = 6'h11;
-  localparam CTRL_MKM_RD_STATUS  = 6'h12;
-  localparam CTRL_MKM_RD_END     = 6'h13;
-
-  localparam CTRL_MKM_WR_START   = 6'h18;
-  localparam CTRL_MKM_WR_WAIT0   = 6'h19;
-  localparam CTRL_MKM_WR_END     = 6'h1a;
-
-  // API for mkm used by the core.
-  localparam MKM_ADDR_CTRL        = 8'h08;
-  localparam MKM_CTRL_READ_BIT    = 0;
-  localparam MKM_CTRL_WRITE_BIT   = 1;
-  localparam MKM_ADDR_STATUS      = 8'h09;
-  localparam MKM_STATUS_READY_BIT = 0;
-  localparam MKM_STATUS_VALID_BIT = 1;
-  localparam MKM_ADDR_SCLK_DIV    = 8'h0a;
-  localparam MKM_ADDR_EMEM_ADDR   = 8'h10;
-  localparam MKM_ADDR_EMEM_DATA   = 8'h20;
-
-  // Addresses for storage in the mkm
-  localparam MKM_STATUS_WORD      = 16'h00;
-  localparam MKM_KEY_BASE_WORD    = 16'h04;
-
-  localparam DEFAULT_SCLK_DIV = 16'h0020;
+  localparam CTRL_RESET          = 4'h0;
+  localparam CTRL_IDLE           = 4'h1;
+  localparam CTRL_INIT_WAIT      = 4'h2;
+  localparam CTRL_NEXT_WSTART    = 4'h3;
+  localparam CTRL_NEXT_USTART    = 4'h4;
+  localparam CTRL_NEXT_LOOP0     = 4'h5;
+  localparam CTRL_NEXT_LOOP      = 4'h6;
+  localparam CTRL_NEXT_WAIT      = 4'h7;
+  localparam CTRL_NEXT_UPDATE    = 4'h8;
+  localparam CTRL_NEXT_WCHECK    = 4'h9;
+  localparam CTRL_NEXT_UCHECK    = 4'ha;
+  localparam CTRL_NEXT_FINALIZE  = 4'hb;
+  localparam CTRL_MKM_WAIT       = 4'hc;
 
 
   //----------------------------------------------------------------
@@ -153,8 +130,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
   reg          iteration_ctr_set;
   reg          iteration_ctr_rst;
 
-  reg [5 : 0]  keywrap_core_ctrl_reg;
-  reg [5 : 0]  keywrap_core_ctrl_new;
+  reg [3 : 0]  keywrap_core_ctrl_reg;
+  reg [3 : 0]  keywrap_core_ctrl_new;
   reg          keywrap_core_ctrl_we;
 
 
@@ -167,6 +144,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
   wire           aes_valid;
   reg  [127 : 0] aes_block;
   wire [127 : 0] aes_result;
+  reg [255 : 0]  aes_key;
 
   reg            update_state;
 
@@ -180,7 +158,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
   reg            mkm_write;
   reg            mkm_key_status;
   wire           mkm_ready;
-  wire [255 : 0] mkm_key;
+  wire [255 : 0] mkm_rd_key;
   wire [31 : 0]  mkm_rd_status;
   wire [31 : 0]  mkm_wr_status;
 
@@ -212,7 +190,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
                .init(aes_init),
                .next(aes_next),
 
-               .key(key),
+               .key(aes_key),
                .keylen(keylen),
 
                .block(aes_block),
@@ -235,13 +213,13 @@ module keywrap_core #(parameter MEM_BITS = 11)
                       .init(mkm_init),
                       .read(mkm_read),
                       .write(mkm_write),
-                      .key_status(mkm_key_status),
+                      .key_status(mkey_mstatus),
                       .ready(mkm_ready),
 
                       .wr_status(mkm_wr_status),
                       .rd_status(mkm_rd_status),
                       .wr_key(key),
-                      .rd_key(mkm_key)
+                      .rd_key(mkm_rd_key)
                      );
 
 
@@ -251,7 +229,8 @@ module keywrap_core #(parameter MEM_BITS = 11)
   assign a_result   = a_reg;
   assign ready      = ready_reg;
   assign valid      = valid_reg;
-  assign mstatus    = mkm_status_reg;
+  assign mkey       = mkm_rd_key;
+  assign mstatus    = mkm_rd_status;
 
 
   //----------------------------------------------------------------
@@ -268,7 +247,7 @@ module keywrap_core #(parameter MEM_BITS = 11)
           valid_reg             <= 1'h1;
           block_ctr_reg         <= {(MEM_BITS - 1){1'h0}};
           iteration_ctr_reg     <= 3'h0;
-          keywrap_core_ctrl_reg <= CTRL_IDLE;
+          keywrap_core_ctrl_reg <= CTRL_RESET;
        end
 
       else
@@ -276,9 +255,6 @@ module keywrap_core #(parameter MEM_BITS = 11)
           if (a_we)
             a_reg <= a_new;
 
-          if (mkm_status_we)
-            mkm_status_reg <= mkm_read_data;
-
           if (ready_we)
             ready_reg <= ready_new;
 
@@ -407,6 +383,17 @@ module keywrap_core #(parameter MEM_BITS = 11)
 
     end
 
+  //----------------------------------------------------------------
+  // aes_key_mux
+  //----------------------------------------------------------------
+  always @*
+    begin
+      if (mkey_key)
+        aes_key = mkm_rd_key;
+      else
+        aes_key = key;
+    end
+
 
   //----------------------------------------------------------------
   // keywrap_core_ctrl
@@ -421,6 +408,9 @@ module keywrap_core #(parameter MEM_BITS = 11)
       update_state          = 1'h0;
       aes_init              = 1'h0;
       aes_next              = 1'h0;
+      mkm_init              = 1'h0;
+      mkm_read              = 1'h0;
+      mkm_write             = 1'h0;
       block_ctr_dec         = 1'h0;
       block_ctr_inc         = 1'h0;
       block_ctr_rst         = 1'h0;
@@ -430,18 +420,21 @@ module keywrap_core #(parameter MEM_BITS = 11)
       iteration_ctr_set     = 1'h0;
       iteration_ctr_rst     = 1'h0;
 
-      mkm_init_op           = 1'h0;
-      mkm_read_op           = 1'h0;
-      mkm_write_op          = 1'h0;
-      mkm_sclk_div          = DEFAULT_SCLK_DIV;
-      mkm_addr              = 16'h0;
-      mkm_write_data        = 32'h0;
-
       keywrap_core_ctrl_new = CTRL_IDLE;
       keywrap_core_ctrl_we  = 1'h0;
 
 
       case (keywrap_core_ctrl_reg)
+        CTRL_RESET:
+          begin
+            mkm_init              = 1'h1;
+            ready_new             = 1'h0;
+            ready_we              = 1'h1;
+            keywrap_core_ctrl_new = CTRL_MKM_WAIT;
+            keywrap_core_ctrl_we  = 1'h0;
+          end
+
+
         CTRL_IDLE:
           begin
             if (init)
@@ -472,17 +465,20 @@ module keywrap_core #(parameter MEM_BITS = 11)
 
             if (read)
               begin
+                mkm_write             = 1'h1;
                 ready_new             = 1'h0;
                 ready_we              = 1'h1;
-                keywrap_core_ctrl_new = CTRL_MKM_RD_START;
+                mkm_read              = 1'h1;
+                keywrap_core_ctrl_new = CTRL_MKM_WAIT;
                 keywrap_core_ctrl_we  = 1'h1;
               end
 
             if (write)
               begin
+                mkm_write             = 1'h1;
                 ready_new             = 1'h0;
                 ready_we              = 1'h1;
-                keywrap_core_ctrl_new = CTRL_MKM_WR_START;
+                keywrap_core_ctrl_new = CTRL_MKM_WAIT;
                 keywrap_core_ctrl_we  = 1'h1;
               end
           end
@@ -616,85 +612,19 @@ module keywrap_core #(parameter MEM_BITS = 11)
           end
 
 
-        CTRL_MKM_RD_START:
-          begin
-            mkm_init_op           = 1'h1;
-            keywrap_core_ctrl_new = CTRL_MKM_RD_WAIT0;
-            keywrap_core_ctrl_we  = 1'h1;
-          end
-
-
-        CTRL_MKM_RD_WAIT0:
-          begin
-            if (mkm_ready)
-              // MKM should have been initialized.
-              if (mkey_mstatus)
-                begin
-                  // Read master key from mkm.
-                  keywrap_core_ctrl_new = CTRL_MKM_RD_END;
-                  keywrap_core_ctrl_we  = 1'h1;
-                end
-              else
-                begin
-                  // Read master key status from mkm.
-                  mkm_read_op           = 1'h1;
-                  mkm_addr              = MKM_STATUS_WORD;
-                  keywrap_core_ctrl_new = CTRL_MKM_RD_STATUS;
-                  keywrap_core_ctrl_we  = 1'h1;
-                end
-          end
-
-
-        CTRL_MKM_RD_STATUS:
-          begin
-            if (mkm_ready)
-              begin
-                // status should have been read.
-                mkm_status_we         = 1'h1;
-                keywrap_core_ctrl_new = CTRL_MKM_RD_END;
-                keywrap_core_ctrl_we  = 1'h1;
-              end
-          end
-
-
-        CTRL_MKM_RD_END:
-          begin
-            ready_new             = 1'h1;
-            ready_we              = 1'h1;
-            keywrap_core_ctrl_new = CTRL_IDLE;
-            keywrap_core_ctrl_we  = 1'h1;
-          end
-
-
-        CTRL_MKM_WR_START:
-          begin
-            mkm_init_op           = 1'h1;
-            keywrap_core_ctrl_new = CTRL_MKM_WR_WAIT0;
-            keywrap_core_ctrl_we  = 1'h1;
-          end
-
-
-        CTRL_MKM_WR_WAIT0:
+        CTRL_MKM_WAIT:
           begin
             if (mkm_ready)
               begin
-                keywrap_core_ctrl_new = CTRL_MKM_WR_END;
+                ready_new             = 1'h1;
+                ready_we              = 1'h1;
+                keywrap_core_ctrl_new = CTRL_IDLE;
                 keywrap_core_ctrl_we  = 1'h1;
               end
           end
 
-
-        CTRL_MKM_WR_END:
-          begin
-            ready_new             = 1'h1;
-            ready_we              = 1'h1;
-            keywrap_core_ctrl_new = CTRL_IDLE;
-            keywrap_core_ctrl_we  = 1'h1;
-          end
-
         default:
           begin
-
           end
       endcase // case (keywrap_core_ctrl_reg)
     end // keywrap_core_ctrl
diff --git a/src/rtl/keywrap_mkmif.v b/src/rtl/keywrap_mkmif.v
index 082173b..ad2121e 100644
--- a/src/rtl/keywrap_mkmif.v
+++ b/src/rtl/keywrap_mkmif.v
@@ -171,11 +171,11 @@ module keywrap_mkmif (
       if (!reset_n)
         begin
           for (i = 0 ; i < 8 ; i = i + 1)
-            key[i] <= 32'h0;
+            key_reg[i] <= 32'h0;
 
           ready_reg              <= 1'h1;
           status_reg             <= 32'h0;
-          mkm_address_reg        <= 16'h0;
+          mkm_addr_reg           <= 16'h0;
           mkm_write_data_reg     <= 32'h0;
           key_word_ctr_reg       <= 3'h0;
           keywrap_mkmif_ctrl_reg <= CTRL_IDLE;
@@ -217,8 +217,8 @@ module keywrap_mkmif (
 
       if (key_word_ctr_rst)
         begin
-          iteration_ctr_new = 3'h0;
-          iteration_ctr_we  = 1'h1;
+          key_word_ctr_new = 3'h0;
+          key_word_ctr_we  = 1'h1;
         end
 
       if (key_word_ctr_inc)
@@ -244,7 +244,6 @@ module keywrap_mkmif (
       mkm_init_op            = 1'h0;
       mkm_read_op            = 1'h0;
       mkm_write_op           = 1'h0;
-      mkm_sclk_div           = DEFAULT_SCLK_DIV;
       mkm_addr_new           = 16'h0;
       mkm_addr_we            = 1'h0;
       mkm_write_data_new     = 32'h0;
@@ -328,6 +327,7 @@ module keywrap_mkmif (
           end
 
         CTRL_READ_KEY:
+          begin
             if (key_word_ctr_reg < 8)
               begin
                 mkm_read_op            = 1'h1;
@@ -363,7 +363,7 @@ module keywrap_mkmif (
                 mkm_write_op           = 1'h1;
                 mkm_addr_new           = MKM_STATUS_WORD + {key_word_ctr_reg, 2'h0};
                 mkm_addr_we            = 1'h1;
-                mkm_write_data_new     = key[key_word_ctr_reg * 32 +: 32];
+                mkm_write_data_new     = wr_key[key_word_ctr_reg * 32 +: 32];
                 mkm_write_data_we      = 1'h1;
                 keywrap_mkmif_ctrl_new = CTRL_WRITE_KEY_WAIT;
                 keywrap_mkmif_ctrl_we  = 1'h1;
diff --git a/src/tb/tb_keywrap_core.v b/src/tb/tb_keywrap_core.v
index 27a2e91..07777aa 100644
--- a/src/tb/tb_keywrap_core.v
+++ b/src/tb/tb_keywrap_core.v
@@ -68,6 +68,7 @@ module tb_keywrap_core();
   reg                           tb_write;
   reg                           tb_encdec;
   reg                           tb_mkey_mstatus;
+  reg                           tb_mkey_key;
   wire                          tb_ready;
   wire                          tb_valid;
   reg [(RLEN_BITS - 1) : 0]     tb_rlen;
@@ -107,6 +108,7 @@ module tb_keywrap_core();
                    .read(tb_read),
                    .write(tb_write),
                    .mkey_mstatus(tb_mkey_mstatus),
+                   .mkey_key(tb_mkey_key),
                    .encdec(tb_encdec),
 
                    .ready(tb_ready),
@@ -175,6 +177,7 @@ module tb_keywrap_core();
       tb_write        = 0;
       tb_encdec       = 0;
       tb_mkey_mstatus = 0;
+      tb_mkey_key     = 0;
       tb_rlen         = 13'h0;
       tb_key          = 256'h0;
       tb_status       = 32'h0;