core/rng/trng - True Random Number Generator core implemented in Verilog

Age	Commit message (Expand)	Author
2019-02-08	(1) Silenced linter by adding default case states. (2) Fixed minor nits in he...cleanup	Joachim Strömbergson
2018-10-16	(1) Fixed width definitions and cleaned up constants as part of checking that...HEAD master	Joachim Strömbergson
2015-12-13	whack copyrights	Paul Selkirk
2015-11-17	Harmonize status valid bit with other cores.	Paul Selkirk
2015-11-16	harmonize ctrl and status addresses with other cores	Paul Selkirk
2015-11-14	Merge branch 'config_core_selector'	Paul Selkirk
2015-09-21	Added control FSM states to handle entropy for testing. Nits: Changed to loca...	Joachim Strömbergson
2015-06-10	make cores contiguous, add mixer name/version	Paul Selkirk
2015-04-28	(1) Remove the delayed read for EIM (see core/platform/novena commit 2f58e8f)...	Paul Selkirk
2015-03-26	Minor cleanup: Morged clocked processes. Changed name of api read data hold r...	Joachim Strömbergson
2015-03-25	streamline(?) api_mux, register data for eim output	Paul Selkirk
2014-11-20	Updates after linting.	Joachim Strömbergson
2014-11-20	(1) Reducing timepout for entropy sources. Updated interface for sha-512 to m...	Joachim Strömbergson
2014-10-02	Updating trng to debugged version.	Joachim Strömbergson
2014-09-27	Adding debug port for mixer and csprng. In the csprng the debug_update will t...	Joachim Strömbergson
2014-09-26	Updating source to the latest and greatest. In this version the entropy sourc...	Joachim Strömbergson
2014-09-11	Update after completion of rtl and debug of rtl using the updated testbench. ...	Joachim Strömbergson
2014-09-11	Adding initial versions of rtl and tb for the mixer.	Joachim Strömbergson