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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-10-16 11:13:50 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-10-16 11:13:50 +0200 |
| commit | e786303f0d2778f7c26cbb443831823c82429205 (patch) | |
| tree | f8e9ff5c14890ed309a643b3e857c0d52a33c53c /src/rtl/trng_mixer.v | |
| parent | 6397d9766e802b2fba115a47e0f0561fcc7e828f (diff) | |
(1) Fixed width definitions and cleaned up constants as part of checking that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint.HEADmaster
Diffstat (limited to 'src/rtl/trng_mixer.v')
| -rw-r--r-- | src/rtl/trng_mixer.v | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v index 06e3323..1a70e27 100644 --- a/src/rtl/trng_mixer.v +++ b/src/rtl/trng_mixer.v @@ -225,8 +225,6 @@ module trng_mixer( reg restart_reg; reg restart_new; - reg [31 : 0] tmp_read_data; - //---------------------------------------------------------------- // Wires. @@ -254,6 +252,8 @@ module trng_mixer( reg tmp_error; + reg [31 : 0] tmp_read_data; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -319,45 +319,45 @@ module trng_mixer( begin if (!reset_n) begin - block00_reg <= 32'h00000000; - block01_reg <= 32'h00000000; - block02_reg <= 32'h00000000; - block03_reg <= 32'h00000000; - block04_reg <= 32'h00000000; - block05_reg <= 32'h00000000; - block06_reg <= 32'h00000000; - block07_reg <= 32'h00000000; - block08_reg <= 32'h00000000; - block09_reg <= 32'h00000000; - block10_reg <= 32'h00000000; - block11_reg <= 32'h00000000; - block12_reg <= 32'h00000000; - block13_reg <= 32'h00000000; - block14_reg <= 32'h00000000; - block15_reg <= 32'h00000000; - block16_reg <= 32'h00000000; - block17_reg <= 32'h00000000; - block18_reg <= 32'h00000000; - block19_reg <= 32'h00000000; - block20_reg <= 32'h00000000; - block21_reg <= 32'h00000000; - block22_reg <= 32'h00000000; - block23_reg <= 32'h00000000; - block24_reg <= 32'h00000000; - block25_reg <= 32'h00000000; - block26_reg <= 32'h00000000; - block27_reg <= 32'h00000000; - block28_reg <= 32'h00000000; - block29_reg <= 32'h00000000; - block30_reg <= 32'h00000000; - block31_reg <= 32'h00000000; - init_done_reg <= 0; - word_ctr_reg <= 5'h00; - seed_syn_reg <= 0; - enable_reg <= 1; - restart_reg <= 0; + block00_reg <= 32'h0; + block01_reg <= 32'h0; + block02_reg <= 32'h0; + block03_reg <= 32'h0; + block04_reg <= 32'h0; + block05_reg <= 32'h0; + block06_reg <= 32'h0; + block07_reg <= 32'h0; + block08_reg <= 32'h0; + block09_reg <= 32'h0; + block10_reg <= 32'h0; + block11_reg <= 32'h0; + block12_reg <= 32'h0; + block13_reg <= 32'h0; + block14_reg <= 32'h0; + block15_reg <= 32'h0; + block16_reg <= 32'h0; + block17_reg <= 32'h0; + block18_reg <= 32'h0; + block19_reg <= 32'h0; + block20_reg <= 32'h0; + block21_reg <= 32'h0; + block22_reg <= 32'h0; + block23_reg <= 32'h0; + block24_reg <= 32'h0; + block25_reg <= 32'h0; + block26_reg <= 32'h0; + block27_reg <= 32'h0; + block28_reg <= 32'h0; + block29_reg <= 32'h0; + block30_reg <= 32'h0; + block31_reg <= 32'h0; + init_done_reg <= 1'h0; + word_ctr_reg <= 5'h0; + seed_syn_reg <= 1'h0; + enable_reg <= 1'h1; + restart_reg <= 1'h0; entropy_timeout_reg <= DEFAULT_ENTROPY_TIMEOUT; - entropy_timeout_ctr_reg <= 24'h000000; + entropy_timeout_ctr_reg <= 24'h0; entropy_collect_ctrl_reg <= CTRL_IDLE; mixer_ctrl_reg <= CTRL_IDLE; end |