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authorJoachim StroĢˆmbergson <joachim@secworks.se>2014-09-26 14:55:18 +0200
committerJoachim StroĢˆmbergson <joachim@secworks.se>2014-09-26 14:55:18 +0200
commitf2d1d8430c9ed9923e9cd701744e705f2c91751b (patch)
tree92e2a322c319a46d903776b3d1cc515054ccbacc /src/rtl/trng_mixer.v
parent70d6aac81ec88f8140d5c644d89d3f580c1b3335 (diff)
Updating source to the latest and greatest. In this version the entropy sources works and all modules have correct intterface.
Diffstat (limited to 'src/rtl/trng_mixer.v')
-rw-r--r--src/rtl/trng_mixer.v128
1 files changed, 112 insertions, 16 deletions
diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v
index 37ea6d2..7d398f5 100644
--- a/src/rtl/trng_mixer.v
+++ b/src/rtl/trng_mixer.v
@@ -37,10 +37,19 @@
//======================================================================
module trng_mixer(
- input wire clk,
- input wire reset_n,
+ input wire clk,
+ input wire reset_n,
+
+ input wire cs,
+ input wire we,
+ input wire [7 : 0] address,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data,
+ output wire error,
+
+ input wire discard,
+ input wire test_mode,
- input wire enable,
input wire more_seed,
input wire entropy0_enabled,
@@ -84,6 +93,12 @@ module trng_mixer(
parameter ENTROPY_SRC2 = 4'h5;
parameter ENTROPY_SRC2_ACK = 4'h6;
+ parameter ADDR_MIXER_CTRL = 8'h10;
+ parameter MIXER_CTRL_ENABLE_BIT = 0;
+ parameter MIXER_CTRL_RESTART_BIT = 1;
+
+ parameter ADDR_MIXER_STATUS = 8'h11;
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
@@ -175,6 +190,13 @@ module trng_mixer(
reg init_done_new;
reg init_done_we;
+ reg enable_reg;
+ reg enable_new;
+ reg enable_we;
+
+ reg restart_reg;
+ reg restart_new;
+
//----------------------------------------------------------------
// Wires.
@@ -196,10 +218,16 @@ module trng_mixer(
reg tmp_entropy1_ack;
reg tmp_entropy2_ack;
+ reg [31 : 0] tmp_read_data;
+ reg tmp_error;
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
+ assign read_data = tmp_read_data;
+ assign error = tmp_error;
+
assign seed_syn = seed_syn_reg;
assign seed_data = hash_digest;
@@ -242,8 +270,8 @@ module trng_mixer(
// reg_update
//
// Update functionality for all registers in the core.
- // All registers are positive edge triggered with synchronous
- // active low reset. All registers have write enable.
+ // All registers are positive edge triggered with asynchronous
+ // active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
@@ -284,11 +312,15 @@ module trng_mixer(
init_done_reg <= 0;
word_ctr_reg <= 5'h00;
seed_syn_reg <= 0;
+ enable_reg <= 0;
+ restart_reg <= 0;
entropy_collect_ctrl_reg <= CTRL_IDLE;
mixer_ctrl_reg <= CTRL_IDLE;
end
else
begin
+ restart_reg <= restart_new;
+
if (block00_we)
begin
block00_reg <= muxed_entropy;
@@ -469,6 +501,11 @@ module trng_mixer(
entropy_collect_ctrl_reg <= entropy_collect_ctrl_new;
end
+ if (enable_we)
+ begin
+ enable_reg <= enable_new;
+ end
+
if (mixer_ctrl_we)
begin
mixer_ctrl_reg <= mixer_ctrl_new;
@@ -476,6 +513,65 @@ module trng_mixer(
end
end // reg_update
+
+ //----------------------------------------------------------------
+ // mixer_api_logic
+ //----------------------------------------------------------------
+ always @*
+ begin : mixer_api_logic
+ enable_new = 0;
+ enable_we = 0;
+ restart_reg = 0;
+ restart_new = 0;
+ tmp_read_data = 32'h00000000;
+ tmp_error = 0;
+
+ if (cs)
+ begin
+ if (we)
+ begin
+ // Write operations.
+ case (address)
+ // Write operations.
+ ADDR_MIXER_CTRL:
+ begin
+ enable_new = write_data[MIXER_CTRL_ENABLE_BIT];
+ enable_we = 1;
+ restart_new = write_data[MIXER_CTRL_RESTART_BIT];
+ end
+
+ default:
+ begin
+ tmp_error = 1;
+ end
+ endcase // case (address)
+ end // if (we)
+
+ else
+ begin
+ // Read operations.
+ case (address)
+ // Read operations.
+ ADDR_MIXER_CTRL:
+ begin
+ tmp_read_data = {30'h00000000, restart_reg, enable_reg};
+ end
+
+ ADDR_MIXER_STATUS:
+ begin
+
+ end
+
+ default:
+ begin
+ tmp_error = 1;
+ end
+ endcase // case (address)
+ end
+ end
+ end // mixer_api_logic
+
+
//----------------------------------------------------------------
// entropy_collect_ctrl
//
@@ -509,7 +605,7 @@ module trng_mixer(
ENTROPY_SRC0:
begin
- if (!enable)
+ if (!enable_reg)
begin
word_ctr_rst = 1;
entropy_collect_ctrl_new = ENTROPY_IDLE;
@@ -538,7 +634,7 @@ module trng_mixer(
ENTROPY_SRC0_ACK:
begin
tmp_entropy0_ack = 1;
- if (!enable)
+ if (!enable_reg)
begin
word_ctr_rst = 1;
entropy_collect_ctrl_new = ENTROPY_IDLE;
@@ -564,7 +660,7 @@ module trng_mixer(
ENTROPY_SRC1:
begin
- if (!enable)
+ if (!enable_reg)
begin
word_ctr_rst = 1;
entropy_collect_ctrl_new = ENTROPY_IDLE;
@@ -593,7 +689,7 @@ module trng_mixer(
ENTROPY_SRC1_ACK:
begin
tmp_entropy1_ack = 1;
- if (!enable)
+ if (!enable_reg)
begin
word_ctr_rst = 1;
entropy_collect_ctrl_new = ENTROPY_IDLE;
@@ -618,7 +714,7 @@ module trng_mixer(
ENTROPY_SRC2:
begin
- if (!enable)
+ if (!enable_reg)
begin
word_ctr_rst = 1;
entropy_collect_ctrl_new = ENTROPY_IDLE;
@@ -647,7 +743,7 @@ module trng_mixer(
ENTROPY_SRC2_ACK:
begin
tmp_entropy2_ack = 1;
- if (!enable)
+ if (!enable_reg)
begin
word_ctr_rst = 1;
entropy_collect_ctrl_new = ENTROPY_IDLE;
@@ -806,7 +902,7 @@ module trng_mixer(
CTRL_COLLECT:
begin
- if ((!enable))
+ if ((!discard))
begin
mixer_ctrl_new = CTRL_IDLE;
mixer_ctrl_we = 1;
@@ -823,7 +919,7 @@ module trng_mixer(
CTRL_MIX:
begin
- if ((!enable))
+ if ((!discard))
begin
mixer_ctrl_new = CTRL_IDLE;
mixer_ctrl_we = 1;
@@ -845,7 +941,7 @@ module trng_mixer(
CTRL_SYN:
begin
- if ((!enable))
+ if ((!discard))
begin
mixer_ctrl_new = CTRL_IDLE;
mixer_ctrl_we = 1;
@@ -862,7 +958,7 @@ module trng_mixer(
CTRL_ACK:
begin
- if ((!enable))
+ if ((!discard))
begin
mixer_ctrl_new = CTRL_IDLE;
mixer_ctrl_we = 1;
@@ -878,7 +974,7 @@ module trng_mixer(
CTRL_NEXT:
begin
- if ((!enable))
+ if ((!discard))
begin
mixer_ctrl_new = CTRL_IDLE;
mixer_ctrl_we = 1;