(1) Fixed width definitions and cleaned up constants as part of checking that all registers are being reset. (2) Cleaned up tasks and removed timescale directives to silence lint.HEADmaster

8 files changed, 93 insertions, 133 deletions

diff --git a/src/rtl/trng.v b/src/rtl/trng.v
index c10e846..107a0b1 100644
--- a/src/rtl/trng.v
+++ b/src/rtl/trng.v
@@ -341,12 +341,12 @@ module trng(
     begin
       if (!reset_n)
         begin
-          discard_reg            <= 0;
-          test_mode_reg          <= 0;
+          discard_reg            <= 1'h0;
+          test_mode_reg          <= 1'h0;
           debug_mux_reg          <= DEBUG_CSPRNG;
           debug_delay_reg        <= DEFAULT_DEBUG_DELAY;
           debug_delay_ctr_reg    <= 32'h00000000;
-          debug_out_reg          <= 8'h00;
+          debug_out_reg          <= 8'h0;
         end
       else
         begin
diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index c682f27..872cb1e 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -194,8 +194,6 @@ module trng_csprng(
   reg [3 : 0]   csprng_ctrl_new;
   reg           csprng_ctrl_we;
 
-  reg [31 : 0]  tmp_read_data;
-
 
   //----------------------------------------------------------------
   // Wires.
@@ -218,6 +216,8 @@ module trng_csprng(
 
   wire           muxed_rnd_ack;
 
+  reg [31 : 0]  tmp_read_data;
+
 
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
@@ -281,18 +281,18 @@ module trng_csprng(
     begin
       if (!reset_n)
         begin
-          cipher_key_reg      <= {8{32'h00000000}};
-          cipher_iv_reg       <= {2{32'h00000000}};
-          cipher_ctr_reg      <= {2{32'h00000000}};
-          cipher_block_reg    <= {16{32'h00000000}};
-          block_ctr_reg       <= {2{32'h00000000}};
-          block_stat_ctr_reg  <= {2{32'h00000000}};
-          reseed_stat_ctr_reg <= 32'h00000000;
-          more_seed_reg       <= 0;
-          seed_ack_reg        <= 0;
-          ready_reg           <= 0;
-          enable_reg          <= 1;
-          seed_reg            <= 0;
+          cipher_key_reg      <= 256'h0;
+          cipher_iv_reg       <= 64'h0;
+          cipher_ctr_reg      <= 64'h0;
+          cipher_block_reg    <= 512'h0;
+          block_ctr_reg       <= 64'h0;
+          block_stat_ctr_reg  <= 64'h0;
+          reseed_stat_ctr_reg <= 32'h0;
+          more_seed_reg       <= 1'h0;
+          seed_ack_reg        <= 1'h0;
+          ready_reg           <= 1'h0;
+          enable_reg          <= 1'h1;
+          seed_reg            <= 1'h0;
           num_rounds_reg      <= DEFAULT_NUM_ROUNDS;
           num_blocks_low_reg  <= DEFAULT_NUM_BLOCKS[31 : 0];
           num_blocks_high_reg <= DEFAULT_NUM_BLOCKS[63 : 32];
diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v
index db0a1be..5fbce89 100644
--- a/src/rtl/trng_csprng_fifo.v
+++ b/src/rtl/trng_csprng_fifo.v
@@ -142,20 +142,21 @@ module trng_csprng_fifo(
   // Register update. All registers have asynchronous reset.
   //----------------------------------------------------------------
   always @ (posedge clk or negedge reset_n)
-    begin
+    begin : reg_update
+      integer i;
+
       if (!reset_n)
         begin
-          fifo_mem[00]     <= {16{32'h00000000}};
-          fifo_mem[01]     <= {16{32'h00000000}};
-          fifo_mem[02]     <= {16{32'h00000000}};
-          fifo_mem[03]     <= {16{32'h00000000}};
+          for (i = 0 ; i < FIFO_MAX ; i = i + 1)
+            fifo_mem[i] <= 512'h0;
+
           mux_data_ptr_reg <= 4'h0;
-          rd_ptr_reg       <= {(FIFO_ADDR_BITS){1'b0}};
-          wr_ptr_reg       <= {(FIFO_ADDR_BITS){1'b0}};
-          fifo_ctr_reg     <= {FIFO_ADDR_BITS{1'b0}};
-          rnd_data_reg     <= 32'h00000000;
-          rnd_syn_reg      <= 0;
-          more_data_reg    <= 0;
+          rd_ptr_reg       <= {(FIFO_ADDR_BITS){1'h0}};
+          wr_ptr_reg       <= {(FIFO_ADDR_BITS){1'h0}};
+          fifo_ctr_reg     <= {FIFO_ADDR_BITS{1'h0}};
+          rnd_data_reg     <= 32'h0;
+          rnd_syn_reg      <= 1'h0;
+          more_data_reg    <= 1'h0;
           wr_ctrl_reg      <= WR_IDLE;
           rd_ctrl_reg      <= RD_IDLE;
         end
diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v
index 06e3323..1a70e27 100644
--- a/src/rtl/trng_mixer.v
+++ b/src/rtl/trng_mixer.v
@@ -225,8 +225,6 @@ module trng_mixer(
   reg         restart_reg;
   reg         restart_new;
 
-  reg [31 : 0] tmp_read_data;
-
 
   //----------------------------------------------------------------
   // Wires.
@@ -254,6 +252,8 @@ module trng_mixer(
 
   reg             tmp_error;
 
+  reg [31 : 0] tmp_read_data;
+
 
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
@@ -319,45 +319,45 @@ module trng_mixer(
     begin
       if (!reset_n)
         begin
-          block00_reg              <= 32'h00000000;
-          block01_reg              <= 32'h00000000;
-          block02_reg              <= 32'h00000000;
-          block03_reg              <= 32'h00000000;
-          block04_reg              <= 32'h00000000;
-          block05_reg              <= 32'h00000000;
-          block06_reg              <= 32'h00000000;
-          block07_reg              <= 32'h00000000;
-          block08_reg              <= 32'h00000000;
-          block09_reg              <= 32'h00000000;
-          block10_reg              <= 32'h00000000;
-          block11_reg              <= 32'h00000000;
-          block12_reg              <= 32'h00000000;
-          block13_reg              <= 32'h00000000;
-          block14_reg              <= 32'h00000000;
-          block15_reg              <= 32'h00000000;
-          block16_reg              <= 32'h00000000;
-          block17_reg              <= 32'h00000000;
-          block18_reg              <= 32'h00000000;
-          block19_reg              <= 32'h00000000;
-          block20_reg              <= 32'h00000000;
-          block21_reg              <= 32'h00000000;
-          block22_reg              <= 32'h00000000;
-          block23_reg              <= 32'h00000000;
-          block24_reg              <= 32'h00000000;
-          block25_reg              <= 32'h00000000;
-          block26_reg              <= 32'h00000000;
-          block27_reg              <= 32'h00000000;
-          block28_reg              <= 32'h00000000;
-          block29_reg              <= 32'h00000000;
-          block30_reg              <= 32'h00000000;
-          block31_reg              <= 32'h00000000;
-          init_done_reg            <= 0;
-          word_ctr_reg             <= 5'h00;
-          seed_syn_reg             <= 0;
-          enable_reg               <= 1;
-          restart_reg              <= 0;
+          block00_reg              <= 32'h0;
+          block01_reg              <= 32'h0;
+          block02_reg              <= 32'h0;
+          block03_reg              <= 32'h0;
+          block04_reg              <= 32'h0;
+          block05_reg              <= 32'h0;
+          block06_reg              <= 32'h0;
+          block07_reg              <= 32'h0;
+          block08_reg              <= 32'h0;
+          block09_reg              <= 32'h0;
+          block10_reg              <= 32'h0;
+          block11_reg              <= 32'h0;
+          block12_reg              <= 32'h0;
+          block13_reg              <= 32'h0;
+          block14_reg              <= 32'h0;
+          block15_reg              <= 32'h0;
+          block16_reg              <= 32'h0;
+          block17_reg              <= 32'h0;
+          block18_reg              <= 32'h0;
+          block19_reg              <= 32'h0;
+          block20_reg              <= 32'h0;
+          block21_reg              <= 32'h0;
+          block22_reg              <= 32'h0;
+          block23_reg              <= 32'h0;
+          block24_reg              <= 32'h0;
+          block25_reg              <= 32'h0;
+          block26_reg              <= 32'h0;
+          block27_reg              <= 32'h0;
+          block28_reg              <= 32'h0;
+          block29_reg              <= 32'h0;
+          block30_reg              <= 32'h0;
+          block31_reg              <= 32'h0;
+          init_done_reg            <= 1'h0;
+          word_ctr_reg             <= 5'h0;
+          seed_syn_reg             <= 1'h0;
+          enable_reg               <= 1'h1;
+          restart_reg              <= 1'h0;
           entropy_timeout_reg      <= DEFAULT_ENTROPY_TIMEOUT;
-          entropy_timeout_ctr_reg  <= 24'h000000;
+          entropy_timeout_ctr_reg  <= 24'h0;
           entropy_collect_ctrl_reg <= CTRL_IDLE;
           mixer_ctrl_reg           <= CTRL_IDLE;
         end
diff --git a/src/tb/tb_csprng.v b/src/tb/tb_csprng.v
index 3b4d787..1f4d82e 100644
--- a/src/tb/tb_csprng.v
+++ b/src/tb/tb_csprng.v
@@ -38,12 +38,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_csprng();
@@ -178,7 +172,7 @@ module tb_csprng();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -272,7 +266,7 @@ module tb_csprng();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -289,7 +283,7 @@ module tb_csprng();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -310,7 +304,7 @@ module tb_csprng();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr       = 0;
       error_ctr       = 0;
@@ -396,7 +390,7 @@ module tb_csprng();
   // enable is set. We also starts pulling random data from the
   // csprng to see that it actually emits data as expected.
   //----------------------------------------------------------------
-  task tc1_init_csprng();
+  task tc1_init_csprng;
     begin
       tc_ctr = tc_ctr + 1;
 
@@ -419,7 +413,7 @@ module tb_csprng();
   // TC2: Test that the CSPRNG is reseeded as expected.
   // We set the max block size to a small value and pull data.
   //----------------------------------------------------------------
-  task tc2_reseed_csprng();
+  task tc2_reseed_csprng;
     begin
       tc_ctr = tc_ctr + 1;
 
diff --git a/src/tb/tb_csprng_fifo.v b/src/tb/tb_csprng_fifo.v
index a2db466..6ceeba5 100644
--- a/src/tb/tb_csprng_fifo.v
+++ b/src/tb/tb_csprng_fifo.v
@@ -37,12 +37,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_csprng_fifo();
@@ -138,7 +132,7 @@ module tb_csprng_fifo();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -166,7 +160,7 @@ module tb_csprng_fifo();
   //
   // Dump the state of the fifo when needed.
   //----------------------------------------------------------------
-  task dump_fifo();
+  task dump_fifo;
     begin
       $display("contents of the fifo");
       $display("--------------------");
@@ -181,28 +175,11 @@ module tb_csprng_fifo();
 
 
   //----------------------------------------------------------------
-  // gen_csprng_data
-  //
-  // Generate test data with distinct patterns as requested
-  // by the dut.
-  //----------------------------------------------------------------
-//  always @ (posedge tb_more_data)
-//    begin
-//      for (i = 0 ; i < 16 ; i = i + 1)
-//        tb_csprng_data[i * 32 +: 32] = tb_csprng_data[i * 32 +: 32] + 32'h10101010;
-//
-//      tb_csprng_data_valid = 1'b1;
-//      #(2 * CLK_PERIOD);
-//      tb_csprng_data_valid = 1'b0;
-//    end
-
-
-  //----------------------------------------------------------------
   // reset_dut()
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -219,7 +196,7 @@ module tb_csprng_fifo();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -240,7 +217,7 @@ module tb_csprng_fifo();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr       = 0;
       error_ctr       = 0;
@@ -269,7 +246,7 @@ module tb_csprng_fifo();
   //
   // Wait for the DUT to signal that it wants more data.
   //----------------------------------------------------------------
-  task wait_more_data();
+  task wait_more_data;
     begin
       while (!tb_more_data)
         #(CLK_PERIOD);
@@ -341,7 +318,7 @@ module tb_csprng_fifo();
   //
   // read a 32 bit data word from the fifo.
   //----------------------------------------------------------------
-  task read_w32();
+  task read_w32;
     begin
       $display("*** Reading from the fifo: 0x%08x", tb_rnd_data);
       tb_rnd_ack = 1;
@@ -359,7 +336,7 @@ module tb_csprng_fifo();
   // extracts 32-bit words and checks that we get the correct
   // words all the time.
   //----------------------------------------------------------------
-  task fifo_test();
+  task fifo_test;
     reg [7 : 0] i;
     reg [7 : 0] j;
 
diff --git a/src/tb/tb_mixer.v b/src/tb/tb_mixer.v
index 3964197..c0f428c 100644
--- a/src/tb/tb_mixer.v
+++ b/src/tb/tb_mixer.v
@@ -37,12 +37,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_mixer();
@@ -178,7 +172,7 @@ module tb_mixer();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -243,7 +237,7 @@ module tb_mixer();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -260,7 +254,7 @@ module tb_mixer();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -281,7 +275,7 @@ module tb_mixer();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr           = 0;
       error_ctr           = 0;
@@ -321,7 +315,7 @@ module tb_mixer();
   // A simple first testcase that tries to make the DUT generate
   // a number of seeds based on entropy from source 0 and 2.
   //----------------------------------------------------------------
-  task tc1_gen_seeds();
+  task tc1_gen_seeds;
     begin
       $display("*** Starting TC1: Setting continious seed generation.");
       tb_entropy0_enabled = 1;
diff --git a/src/tb/tb_trng.v b/src/tb/tb_trng.v
index 38d2559..16d88de 100644
--- a/src/tb/tb_trng.v
+++ b/src/tb/tb_trng.v
@@ -37,12 +37,6 @@
 //======================================================================
 
 //------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
-
-//------------------------------------------------------------------
 // Test module.
 //------------------------------------------------------------------
 module tb_trng();
@@ -182,7 +176,7 @@ module tb_trng();
   //
   // Dump the state of the dump when needed.
   //----------------------------------------------------------------
-  task dump_dut_state();
+  task dump_dut_state;
     begin
       $display("cycle: 0x%016x", cycle_ctr);
       $display("State of DUT");
@@ -247,7 +241,7 @@ module tb_trng();
   //
   // Toggle reset to put the DUT into a well known state.
   //----------------------------------------------------------------
-  task reset_dut();
+  task reset_dut;
     begin
       $display("*** Toggle reset.");
       tb_reset_n = 0;
@@ -264,7 +258,7 @@ module tb_trng();
   //
   // Display the accumulated test results.
   //----------------------------------------------------------------
-  task display_test_results();
+  task display_test_results;
     begin
       if (error_ctr == 0)
         begin
@@ -285,7 +279,7 @@ module tb_trng();
   // Initialize all counters and testbed functionality as well
   // as setting the DUT inputs to defined values.
   //----------------------------------------------------------------
-  task init_sim();
+  task init_sim;
     begin
       cycle_ctr          = 0;
       error_ctr          = 0;
@@ -310,7 +304,7 @@ module tb_trng();
   // A simple first testcase that tries to make the DUT generate
   // a number of random values.
   //----------------------------------------------------------------
-  task tc1_gen_rnd();
+  task tc1_gen_rnd;
     reg [31 : 0] i;
 
     begin