diff options
Diffstat (limited to 'src/tb/tb_trng.v')
| -rw-r--r-- | src/tb/tb_trng.v | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/src/tb/tb_trng.v b/src/tb/tb_trng.v index 38d2559..16d88de 100644 --- a/src/tb/tb_trng.v +++ b/src/tb/tb_trng.v @@ -37,12 +37,6 @@ //====================================================================== //------------------------------------------------------------------ -// Simulator directives. -//------------------------------------------------------------------ -`timescale 1ns/100ps - - -//------------------------------------------------------------------ // Test module. //------------------------------------------------------------------ module tb_trng(); @@ -182,7 +176,7 @@ module tb_trng(); // // Dump the state of the dump when needed. //---------------------------------------------------------------- - task dump_dut_state(); + task dump_dut_state; begin $display("cycle: 0x%016x", cycle_ctr); $display("State of DUT"); @@ -247,7 +241,7 @@ module tb_trng(); // // Toggle reset to put the DUT into a well known state. //---------------------------------------------------------------- - task reset_dut(); + task reset_dut; begin $display("*** Toggle reset."); tb_reset_n = 0; @@ -264,7 +258,7 @@ module tb_trng(); // // Display the accumulated test results. //---------------------------------------------------------------- - task display_test_results(); + task display_test_results; begin if (error_ctr == 0) begin @@ -285,7 +279,7 @@ module tb_trng(); // Initialize all counters and testbed functionality as well // as setting the DUT inputs to defined values. //---------------------------------------------------------------- - task init_sim(); + task init_sim; begin cycle_ctr = 0; error_ctr = 0; @@ -310,7 +304,7 @@ module tb_trng(); // A simple first testcase that tries to make the DUT generate // a number of random values. //---------------------------------------------------------------- - task tc1_gen_rnd(); + task tc1_gen_rnd; reg [31 : 0] i; begin |