diff options
Diffstat (limited to 'src/rtl/trng_csprng_fifo.v')
| -rw-r--r-- | src/rtl/trng_csprng_fifo.v | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/src/rtl/trng_csprng_fifo.v b/src/rtl/trng_csprng_fifo.v index db0a1be..5fbce89 100644 --- a/src/rtl/trng_csprng_fifo.v +++ b/src/rtl/trng_csprng_fifo.v @@ -142,20 +142,21 @@ module trng_csprng_fifo( // Register update. All registers have asynchronous reset. //---------------------------------------------------------------- always @ (posedge clk or negedge reset_n) - begin + begin : reg_update + integer i; + if (!reset_n) begin - fifo_mem[00] <= {16{32'h00000000}}; - fifo_mem[01] <= {16{32'h00000000}}; - fifo_mem[02] <= {16{32'h00000000}}; - fifo_mem[03] <= {16{32'h00000000}}; + for (i = 0 ; i < FIFO_MAX ; i = i + 1) + fifo_mem[i] <= 512'h0; + mux_data_ptr_reg <= 4'h0; - rd_ptr_reg <= {(FIFO_ADDR_BITS){1'b0}}; - wr_ptr_reg <= {(FIFO_ADDR_BITS){1'b0}}; - fifo_ctr_reg <= {FIFO_ADDR_BITS{1'b0}}; - rnd_data_reg <= 32'h00000000; - rnd_syn_reg <= 0; - more_data_reg <= 0; + rd_ptr_reg <= {(FIFO_ADDR_BITS){1'h0}}; + wr_ptr_reg <= {(FIFO_ADDR_BITS){1'h0}}; + fifo_ctr_reg <= {FIFO_ADDR_BITS{1'h0}}; + rnd_data_reg <= 32'h0; + rnd_syn_reg <= 1'h0; + more_data_reg <= 1'h0; wr_ctrl_reg <= WR_IDLE; rd_ctrl_reg <= RD_IDLE; end |