| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-03-17 | Rearrange cores. | Paul Selkirk | |
| 2014-05-09 | Adding new prebuilt FPGA with uart that supports change of bitrate. | Joachim Strömbergson | |
| 2014-05-07 | Adding prebuilt coretest_hashes that includes SHA-512. | Joachim Strömbergson | |
| 2014-05-07 | Update of prebuilt FPGA configuration with new coretest. | Joachim Strömbergson | |
| 2014-03-17 | Adding project, assignment and clock setup files for Quartus and the TerasIC ↵ | Joachim Strömbergson | |
| C5G board. | |||
| 2014-03-17 | Adding bitstream file for coretest_hashes on the TerasIC C5G board. | Joachim Strömbergson | |
| 2014-03-13 | Adding Makefile to build the coretest_hashes subsystem. | Joachim Strömbergson | |
 |
index : core/platform/terasic_c5g | |
| Platform-specific files for the TerasIC C5G development board | git repositories |
| aboutsummaryrefslogtreecommitdiff |