Change reset to active-low.

6 files changed, 22 insertions, 22 deletions

diff --git a/core_selector/src/rtl/cipher_selector.v b/core_selector/src/rtl/cipher_selector.v
index 654ab4e..a8de37e 100644
--- a/core_selector/src/rtl/cipher_selector.v
+++ b/core_selector/src/rtl/cipher_selector.v
@@ -42,7 +42,7 @@
 module cipher_selector
   (
    input wire           sys_clk,
-   input wire           sys_rst,
+   input wire           sys_rst_n,
    input wire           sys_ena,
 
    input wire [13: 0]   sys_eim_addr,
@@ -88,7 +88,7 @@ module cipher_selector
    aes aes_inst
      (
       .clk(sys_clk),
-      .reset_n(~sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(enable_aes & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),
@@ -112,7 +112,7 @@ module cipher_selector
    chacha chacha_inst
      (
       .clk(sys_clk),
-      .reset_n(~sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(enable_chacha & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),
diff --git a/core_selector/src/rtl/core_selector.v b/core_selector/src/rtl/core_selector.v
index 79c1fa4..fad4104 100644
--- a/core_selector/src/rtl/core_selector.v
+++ b/core_selector/src/rtl/core_selector.v
@@ -42,7 +42,7 @@
 module core_selector
   (
    input wire          sys_clk,
-   input wire          sys_rst,
+   input wire          sys_rst_n,
 
    input wire [16: 0]  sys_eim_addr,
    input wire          sys_eim_wr,
@@ -108,7 +108,7 @@ module core_selector
    global_selector globals
      (
       .sys_clk(sys_clk),
-      .sys_rst(sys_rst),
+      .sys_rst_n(sys_rst_n),
       .sys_ena(segment_enable_globals),
 
       .sys_eim_addr(addr_segment_int),
@@ -132,7 +132,7 @@ module core_selector
    hash_selector hashes
      (
       .sys_clk(sys_clk),
-      .sys_rst(sys_rst),
+      .sys_rst_n(sys_rst_n),
       .sys_ena(segment_enable_hashes),
 
       .sys_eim_addr(addr_segment_int),
@@ -157,7 +157,7 @@ module core_selector
    rng_selector rngs
      (
       .sys_clk(sys_clk),
-      .sys_rst(sys_rst),
+      .sys_rst_n(sys_rst_n),
       .sys_ena(segment_enable_rngs),
 
       .sys_eim_addr(addr_segment_int),
@@ -183,7 +183,7 @@ module core_selector
    cipher_selector ciphers
      (
       .sys_clk(sys_clk),
-      .sys_rst(sys_rst),
+      .sys_rst_n(sys_rst_n),
       .sys_ena(segment_enable_ciphers),
 
       .sys_eim_addr(addr_segment_int),
@@ -206,7 +206,7 @@ module core_selector
    math_selector maths
      (
       .sys_clk(sys_clk),
-      .sys_rst(sys_rst),
+      .sys_rst_n(sys_rst_n),
       .sys_ena(segment_enable_math),
 
       .sys_eim_addr(addr_segment_int),
diff --git a/core_selector/src/rtl/global_selector.v b/core_selector/src/rtl/global_selector.v
index 523cc9b..2b9e20a 100644
--- a/core_selector/src/rtl/global_selector.v
+++ b/core_selector/src/rtl/global_selector.v
@@ -42,7 +42,7 @@
 module global_selector
   (
    input wire           sys_clk,
-   input wire           sys_rst,
+   input wire           sys_rst_n,
    input wire           sys_ena,
 
    input wire [13: 0]   sys_eim_addr,
@@ -80,7 +80,7 @@ module global_selector
    board_regs board_regs
      (
       .clk(sys_clk),
-      .rst(sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(enable_board & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),
@@ -102,7 +102,7 @@ module global_selector
    comm_regs comm_regs
      (
       .clk(sys_clk),
-      .rst(sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(enable_comm & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),
diff --git a/core_selector/src/rtl/hash_selector.v b/core_selector/src/rtl/hash_selector.v
index ad6793e..81fac7d 100644
--- a/core_selector/src/rtl/hash_selector.v
+++ b/core_selector/src/rtl/hash_selector.v
@@ -42,7 +42,7 @@
 module hash_selector
   (
    input wire           sys_clk,
-   input wire           sys_rst,
+   input wire           sys_rst_n,
    input wire           sys_ena,
 
    input wire [13 : 0]  sys_eim_addr,
@@ -82,7 +82,7 @@ XXX move to `define in wrapper core??
     * 3. Add instantiation of your new core after all existing cores
     *    surrounded by conditional synthesis directives.
     *    You also need a 32-bit output (read data) bus for your core and an
-    *    enable flag. Note that sys_rst in an active-high sync reset signal.
+    *    enable flag. Note that sys_rst_n in an active-low sync reset signal.
     *
     *   `ifdef USE_CORE_XXX
     *       wire [31: 0]    read_data_xxx;
@@ -90,7 +90,7 @@ XXX move to `define in wrapper core??
     *       xxx xxx_inst
     *       (
     *       .clk(sys_clk),
-    *       .reset_n(~sys_rst),
+    *       .reset_n(sys_rst_n),
     *       .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)),
     *       .we(sys_eim_wr),
     *       .address(addr_core_reg),
@@ -149,7 +149,7 @@ XXX move to `define in wrapper core??
    sha1 sha1_inst
      (
       .clk(sys_clk),
-      .reset_n(~sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),
@@ -173,7 +173,7 @@ XXX move to `define in wrapper core??
    sha256 sha256_inst
      (
       .clk(sys_clk),
-      .reset_n(~sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),
@@ -197,7 +197,7 @@ XXX move to `define in wrapper core??
    sha512 sha512_inst
      (
       .clk(sys_clk),
-      .reset_n(~sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),
diff --git a/core_selector/src/rtl/math_selector.v b/core_selector/src/rtl/math_selector.v
index b47a433..c967715 100644
--- a/core_selector/src/rtl/math_selector.v
+++ b/core_selector/src/rtl/math_selector.v
@@ -43,7 +43,7 @@
 module math_selector
   (
    input wire           sys_clk,
-   input wire           sys_rst,
+   input wire           sys_rst_n,
    input wire           sys_ena,
 
    input wire [13: 0]   sys_eim_addr,
@@ -86,7 +86,7 @@ module math_selector
    modexp modexp_inst
      (
       .clk(sys_clk),
-      .reset_n(~sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(enable_modexp & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),
diff --git a/core_selector/src/rtl/rng_selector.v b/core_selector/src/rtl/rng_selector.v
index 9dd0330..82f0e9b 100644
--- a/core_selector/src/rtl/rng_selector.v
+++ b/core_selector/src/rtl/rng_selector.v
@@ -42,7 +42,7 @@
 module rng_selector
   (
    input wire           sys_clk,
-   input wire           sys_rst,
+   input wire           sys_rst_n,
    input wire           sys_ena,
 
    input wire [13: 0]   sys_eim_addr,
@@ -63,7 +63,7 @@ module rng_selector
    trng trng_inst
      (
       .clk(sys_clk),
-      .reset_n(~sys_rst),
+      .reset_n(sys_rst_n),
 
       .cs(sys_ena & (sys_eim_rd | sys_eim_wr)),
       .we(sys_eim_wr),