diff options
Diffstat (limited to 'core_selector/src/rtl/hash_selector.v')
| -rw-r--r-- | core_selector/src/rtl/hash_selector.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/core_selector/src/rtl/hash_selector.v b/core_selector/src/rtl/hash_selector.v index ad6793e..81fac7d 100644 --- a/core_selector/src/rtl/hash_selector.v +++ b/core_selector/src/rtl/hash_selector.v @@ -42,7 +42,7 @@ module hash_selector ( input wire sys_clk, - input wire sys_rst, + input wire sys_rst_n, input wire sys_ena, input wire [13 : 0] sys_eim_addr, @@ -82,7 +82,7 @@ XXX move to `define in wrapper core?? * 3. Add instantiation of your new core after all existing cores * surrounded by conditional synthesis directives. * You also need a 32-bit output (read data) bus for your core and an - * enable flag. Note that sys_rst in an active-high sync reset signal. + * enable flag. Note that sys_rst_n in an active-low sync reset signal. * * `ifdef USE_CORE_XXX * wire [31: 0] read_data_xxx; @@ -90,7 +90,7 @@ XXX move to `define in wrapper core?? * xxx xxx_inst * ( * .clk(sys_clk), - * .reset_n(~sys_rst), + * .reset_n(sys_rst_n), * .cs(enable_xxx & (sys_eim_rd | sys_eim_wr)), * .we(sys_eim_wr), * .address(addr_core_reg), @@ -149,7 +149,7 @@ XXX move to `define in wrapper core?? sha1 sha1_inst ( .clk(sys_clk), - .reset_n(~sys_rst), + .reset_n(sys_rst_n), .cs(enable_sha1 & (sys_eim_rd | sys_eim_wr)), .we(sys_eim_wr), @@ -173,7 +173,7 @@ XXX move to `define in wrapper core?? sha256 sha256_inst ( .clk(sys_clk), - .reset_n(~sys_rst), + .reset_n(sys_rst_n), .cs(enable_sha256 & (sys_eim_rd | sys_eim_wr)), .we(sys_eim_wr), @@ -197,7 +197,7 @@ XXX move to `define in wrapper core?? sha512 sha512_inst ( .clk(sys_clk), - .reset_n(~sys_rst), + .reset_n(sys_rst_n), .cs(enable_sha512 & (sys_eim_rd | sys_eim_wr)), .we(sys_eim_wr), |