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authorPaul Selkirk <paul@psgd.org>2019-01-22 19:39:09 -0500
committerPaul Selkirk <paul@psgd.org>2019-01-22 20:01:10 -0500
commit36e8f3dc6cb62ecc53f36dfd798bf8196c4c758b (patch)
treeaaceb309ab627199a508a2764aa7d3e0c6598197 /build/Makefile
parentaf8de11dc0b5e138ae78be9d6b7bfa5724be3141 (diff)
Cherry-pick 8cd28d0/fe3d53c: Added `include directories to Makefile.
Diffstat (limited to 'build/Makefile')
-rw-r--r--build/Makefile4
1 files changed, 4 insertions, 0 deletions
diff --git a/build/Makefile b/build/Makefile
index 4328fbd..6634de7 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings$(WORD_SIZE).sh
ucf ?= ../ucf/$(project).ucf
+# Verilog include directories, if needed
+
+vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode
+
all: $(project).bit
# Build the default core_selector if it doesn't already exist.