From 36e8f3dc6cb62ecc53f36dfd798bf8196c4c758b Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Tue, 22 Jan 2019 19:39:09 -0500
Subject: Cherry-pick 8cd28d0/fe3d53c: Added `include directories to Makefile.

---
 build/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'build/Makefile')

diff --git a/build/Makefile b/build/Makefile
index 4328fbd..6634de7 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -18,6 +18,10 @@ isedir		= /opt/Xilinx/14.7/ISE_DS
 xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
 ucf		?= ../ucf/$(project).ucf
 
+# Verilog include directories, if needed
+
+vlgincdir	= $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode
+
 all:	$(project).bit
 
 # Build the default core_selector if it doesn't already exist.
-- 
cgit v1.2.3