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| author | Paul Selkirk <paul@psgd.org> | 2019-01-22 19:39:09 -0500 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2019-01-22 20:01:10 -0500 |
| commit | 36e8f3dc6cb62ecc53f36dfd798bf8196c4c758b (patch) | |
| tree | aaceb309ab627199a508a2764aa7d3e0c6598197 | |
| parent | af8de11dc0b5e138ae78be9d6b7bfa5724be3141 (diff) | |
Cherry-pick 8cd28d0/fe3d53c: Added `include directories to Makefile.
| -rw-r--r-- | build/Makefile | 4 | ||||
| -rw-r--r-- | build/xilinx.mk | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/build/Makefile b/build/Makefile index 4328fbd..6634de7 100644 --- a/build/Makefile +++ b/build/Makefile @@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh ucf ?= ../ucf/$(project).ucf +# Verilog include directories, if needed + +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode + all: $(project).bit # Build the default core_selector if it doesn't already exist. diff --git a/build/xilinx.mk b/build/xilinx.mk index abeff7b..76d0110 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -152,6 +152,7 @@ $(project).scr: $(optfile) $(mkfiles) ./xilinx.opt echo "-top $(top_module)" >> $@ echo "-ifn $(project).prj" >> $@ echo "-ofn $(project).ngc" >> $@ + echo "-vlgincdir {$(vlgincdir)}" >> $@ cat ./xilinx.opt $(optfile) >> $@ junk += $(project).scr |