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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-11-20 14:34:36 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-11-20 14:34:36 +0300 |
| commit | 157d5dedd90fede9ea392e2aeda6562d839a30e1 (patch) | |
| tree | d9966604e0a1f0820abe85f780ca9916e23ff729 /modexpng_fpga_model.py | |
| parent | 189dfd62e2385aa2f36c6283628b8d9285c49647 (diff) | |
Small change to the reductor module to try to get past 180 MHz. Previously BRAM
outputs were going directry into a LUT-based ternary adder which was causing
timing problems. Added a layer of flip-flops, so instead of BRAM -> LUT -> FF
we have BRAM -> FF -> LUT -> FF. This increases core latency by
(number_of_supporting_modular_multiplications + number_of_exponent_bits) ticks.
Diffstat (limited to 'modexpng_fpga_model.py')
0 files changed, 0 insertions, 0 deletions