Removed the latch accidentally created while pipelining the uOP engine module.

The FSM previously had four states encoded using two bits, so the next state
logic didn't have a default case, since all the possible states were used.
Addition of the fifth state required one more state bit, so the FSM now has
five states out eight possible and a default case is thus necessary.

0 files changed, 0 insertions, 0 deletions