path: root/rtl/modexpng_sdp_36k_x32_x16_wrapper_generic.v

//======================================================================
//
// Copyright: 2019, The Commons Conservancy Cryptech Project
// SPDX-License-Identifier: BSD-3-Clause
//
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// modification, are permitted provided that the following conditions
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//   notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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//   documentation and/or other materials provided with the distribution.
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//======================================================================

module modexpng_sdp_36k_x32_x16_wrapper_generic
(
    clk, clk_bus,
    
    ena, wea,
    addra, dina,
    
    enb,
    addrb, doutb
);


    //
    // Headers
    //
    `include "modexpng_parameters.vh"


    //
    // Ports
    //
    input                                     clk;
    input                                     clk_bus;
    
    input                                     ena;
    input                                     wea;
    input  [BANK_ADDR_W + OP_ADDR_W     -1:0] addra;
    input  [              WORD_W        -1:0] dina;
    
    input                                     enb;
    input  [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addrb;
    output [              BUS_DATA_W    -1:0] doutb;

    
    //
    // Memory
    //
    reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1];
   
    //
    // Write Port
    //
    wire [BANK_ADDR_W + BUS_OP_ADDR_W -2:0] addra_msb = addra[BANK_ADDR_W + BUS_OP_ADDR_W -1:1];
    wire                                    addra_lsb = addra[0];
    
    always @(posedge clk)
        //
        if (ena && wea) begin
           if (addra_lsb) mem[addra_msb][BUS_DATA_W-1:WORD_W] <= dina;
           else           mem[addra_msb][    WORD_W-1:     0] <= dina;
        end
            
    //
    // Read Port
    //
    reg [BUS_DATA_W -1:0] doutb_reg;
    
    assign doutb = doutb_reg;
        
    always @(posedge clk_bus)
        //
        if (enb)
            doutb_reg <= mem[addrb];
            
    
endmodule